counter6.vhd

计数器、频率计、优先编码器、数码管扫描电路、数据选择器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY counter6 IS 
  PORT(clk,clr:IN STD_LOGIC;
        oc:OUT STD_LOGIC;
     y0,y1:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END counter6;
ARCHITECTURE behave OF counter6 IS
SIGNAL q:STD_LOGIC;
   BEGIN
a:PROCESS(clr,clk)
  VARIABLE count:STD_LOGIC_VECTOR(3 DOWNTO 0);
  VARIABLE q0:STD_LOGIC;
    BEGIN
    IF clk'EVENT AND clk='1' THEN 
       IF clr='0' THEN count:=(OTHERS=>'0');
          ELSIF clr='1' THEN
             IF count<9 THEN count:=count+1; q0:='0';

               ELSIF count=9 THEN count:=(OTHERS=>'0');q0:='1';
                 ELSE count:=(OTHERS=>'0');q0:='0';
             END IF;
       END IF;
    END IF;
    q<=q0;
    y0<=count;
  END PROCESS;

b:PROCESS(clr,q)
  VARIABLE count:STD_LOGIC_VECTOR(3 DOWNTO 0);
  VARIABLE q0:STD_LOGIC;
     BEGIN
    IF clr='0' THEN count:=(OTHERS=>'0');
     ELSIF q'EVENT AND q='1' THEN 
       
       IF clr='1' THEN 
          IF count<5 THEN count:=count+1;q0:='0';
            ELSIF count=5 THEN count:=(OTHERS=>'0'); q0:='1';
              ELSE count:=(OTHERS=>'0');q0:='0';
          END IF;oc<=q0;
       END IF;
     END IF;
     y1<=count;
     END PROCESS;
END behave;