plj.vhd.bak

基于vhdl 的数字频率计的设计源程序及工程文件

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fen is
 port(clk:in std_logic;
      q:out std_logic);
 end fen;
architecture rtl of fen is
signal cq:std_logic;
signal dq:std_logic;
begin
p1:process(clk)
variable cnt:integer range 0 to 1000;
begin
if clk'event and clk='1' then
 if  cnt<1000 then
  cnt:=cnt+1;cq<='0';
  else
  cnt:=0;
 cq<='1';
end if;
end if;
end process p1 ;
p2: process (cq)
 variable  d0:integer;
 begin
 if cq'event and cq='1'then
  if d0<1 then
 d0:=d0+1;dq<='1';
 else dq<='0';
 end if;
end if;
end process p2;
q<=dq;
end rtl;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity pilvji is
 port(clr,sig,door:in std_logic;
       alm:out std_logic;
     dian0,q3,q2,q1,q0,dang0 :out std_logic_vector(3 downto 0));
end  pilvji;
architecture rtl of pilvji is
begin
process(door,sig)
variable c0,c1,c2,c3,c4,c5,c6:std_logic_vector(3 downto 0);
begin
if sig'event and sig='1' then
if door='1' then
if c0<"1001" then
   c0:=c0+1;
else c0:="0000"; 
if c1<"1001" then
   c1:=c1+1;
else c1:="0000"; 
if c2<"1001" then
   c2:=c2+1;
else c2:="0000"; 
if c3<"1001" then
   c3:=c3+1;
else c3:="0000"; 
if c4<"1001" then
   c4:=c4+1;
else c4:="0000"; 
 if c5<"1001" then
   c5:=c5+1;
else c5:="0000"; 
if c6<"1001" then
   c6:=c6+1;
else c6:="0000"; 
     alm<='1';
end if;
end if;
end if;
end if;
end if;
end if;
end if;
else
if clr='1' then alm<='0';
end if;
c6:="0000";c5:="0000";c4:="0000";c3:="0000";c2:="0000";c1:="0000";c0:="0000";
end if;
if c6/="0000" then
q3<=c6;q2<=c5;q1<=c4;q0<=c3;dang0<="0100"; dian0<="1000";
elsif c5/="0000" then
q3<=c5;q2<=c4;q1<=c3;q0<=c2;dang0<="0011"; dian0<="0010";
elsif c4/="0000" then
q3<=c4;q2<=c3;q1<=c2;q0<=c1;dang0<="0010"; dian0<="0100";
else
q3<=c3;q2<=c2;q1<=c1;q0<=c0;dang0<="0001"; dian0<="0000";
end if;
end if;
end process;
end rtl;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity lock is
 port(cp:in std_logic;
      a5,a4,a3,a2,a1,a0:in std_logic_vector(3 downto 0);
       m5,m4,m3,m2,m1,m0 :out std_logic_vector(3 downto 0));
end  lock;
architecture rtl of lock is
begin
process(cp)
begin
if cp'event and cp='0' then
m5<=a5;m4<=a4;m3<=a3;m2<=a2;m1<=a1;m0<=a0;
end if;
end process ;
end rtl;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ch is
 port(clk:in std_logic;
       sel:buffer std_logic_vector(2 downto 0);
      dian,e3,e2,e1,e0,dang1:in std_logic_vector(3 downto 0);
      nod :out std_logic;
       tmp:out std_logic_vector(3 downto 0));
end  ch;
architecture rtl of ch is
begin
p1:process(clk)
variable count:std_logic_vector(2 downto 0);
begin
if clk'event and clk='1' then sel<=sel+1;
end if;
end process p1 ;
p2:process(sel)
begin
case sel is
  when "000" =>tmp<=e0; nod<=dian(0);
  when "001" =>tmp<=e1; nod<=dian(1);
  when "010" =>tmp<=e2; nod<=dian(2);
  when "011" =>tmp<=e3; nod<=dian(3);
  when "111" =>tmp<=dang1;
  when  others=> null;
end case;
end process ;
end rtl;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity plj is
port(clk,sig,clr:in std_logic;
     alm:out std_logic;
      node :out std_logic;
      selct:out std_logic_vector(2 downto 0);
      temp:out std_logic_vector(3 downto 0));
end plj;
architecture rtl of plj is
component fen is
port(clk:in std_logic;
       q:out std_logic);
 end component fen;
component pilvji is
port(clr,sig,door:in std_logic;
       alm:out std_logic;
       dian0,q3,q2,q1,q0,dang0 :out std_logic_vector(3 downto 0));       
end component  pilvji;
component lock is
port(cp:in std_logic;
       a5,a4,a3,a2,a1,a0:in std_logic_vector(3 downto 0);
     m5,m4,m3,m2,m1,m0:out std_logic_vector(3 downto 0));
end   component lock;
component ch is
  port( clk:std_logic;
       sel:buffer std_logic_vector(2 downto 0);
       dian,e3,e2,e1,e0,dang1:in std_logic_vector(3 downto 0);
       nod: out std_logic;
       tmp:out std_logic_vector(3 downto 0));
end component ch;
signal b5,b4,b3,b2,b1,b0,h5,h4,h3,h2,h1,h0:std_logic_vector(3 downto 0);
signal d:std_logic;
begin
u1:fen port map(clk=>clk,q=>d);
u2:pilvji port map(clr=>clr,sig=>sig,door=>d,alm=>alm,dian0=>b5,q3=>b4,q2=>b3,q1=>b2,q0=>b1,dang0=>b0);
u3:lock port map(cp=>d,a5=>b5,a4=>b4,a3=>b3,a2=>b2,a1=>b1,a0=>b0,m5=>h5,m4=>h4,m3=>h3,m2=>h2,m1=>h1,m0=>h0);
u4:ch port map( clk=>clk,sel=>selct,dian=>h5,e3=>h4,e2=>h3,e1=>h2,e0=>h1,dang1=>h0,nod=>node,tmp=>temp);
end rtl;