📄 vga_controller.vhd.bak
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity VGA_Controller is
port (
--VGA Side
BLANK : out std_logic;
SYNC : out std_logic;
VGA_CLK : out std_logic;
hs,vs : out std_logic; --行同步、场同步信号
oRed : out std_logic_vector (9 downto 0);
oGreen : out std_logic_vector (9 downto 0);
oBlue : out std_logic_vector (9 downto 0);
--RAM side
-- R,G,B : in std_logic_vector (9 downto 0);
-- addr : out std_logic_vector (18 downto 0);
--Control Signals
reset : in std_logic;
CLK_0 : in std_logic); --75M时钟输入
end entity VGA_Controller;
architecture behave of VGA_Controller is
--VGA
signal CLK : std_logic;
signal rt,gt,bt : std_logic_vector (9 downto 0);
signal hst,vst : std_logic;
signal x : std_logic_vector (9 downto 0); --X坐标
signal y : std_logic_vector (8 downto 0); --Y坐标
begin
BLANK <= '1';
SYNC <= '1';
VGA_CLK <= CLK;
-----------------------------------------------------------------------
process (CLK_0)
begin
if CLK_0'event and CLK_0 = '1' then
CLK <= not CLK;
end if;
end process;
-----------------------------------------------------------------------
process (CLK, reset) --行区间像素数(含消隐区)
begin
if reset = '0' then
x <= (others => '0');
elsif CLK'event and CLK = '1' then
if x = 799 then
x <= (others => '0');
else
x <= x + 1;
end if;
end if;
end process;
-----------------------------------------------------------------------
process (CLK, reset) --场区间行数(含消隐区)
begin
if reset = '1' then
y <= (others => '0');
elsif CLK'event and CLK = '1' then
if x = 799 then
if y = 524 then
y <= (others => '0');
else
y <= y + 1;
end if;
end if;
end if;
end process;
-----------------------------------------------------------------------
process (CLK, reset) --行同步信号产生(同步宽度96,前沿16)
begin
if reset = '1' then
hst <= '1';
elsif CLK'event and CLK = '1' then
if x >= 656 and x < 752 then
hst <= '0';
else
hst <= '1';
end if;
end if;
end process;
-----------------------------------------------------------------------
process (CLK, reset) --场同步信号产生(同步宽度2,前沿10)
begin
if reset = '1' then
vst <= '1';
elsif CLK'event and CLK = '1' then
if y >= 490 and y< 492 then
vst <= '0';
else
vst <= '1';
end if;
end if;
end process;
-----------------------------------------------------------------------
process (CLK, reset) --行同步信号输出
begin
if reset = '1' then
hs <= '0';
elsif CLK'event and CLK = '1' then
hs <= hst;
end if;
end process;
-----------------------------------------------------------------------
process (CLK, reset) --场同步信号输出
begin
if reset = '1' then
vs <= '0';
elsif CLK'event and CLK='1' then
vs <= vst;
end if;
end process;
------------------------------------------------------------------------
-- process (CLK, reset) -- XY坐标定位控制
-- begin
-- if reset = '1' then
-- rt <= (others => '0');
-- gt <= (others => '0');
-- bt <= (others => '0');
-- addr <= (others => '0');
-- elsif CLK'event and CLK='1' then
-- addr <= x&y;
-- rt <= R;
-- gt <= G;
-- bt <= B;
-- end if;
-- end process;
-----------------------------------------------------------------------
-----------------------------------------------------------------------
-----------------------------------------------------------------------
process(reset,clk,x,y) -- XY坐标定位控制
begin
if reset='1' then
rt <= "0000000000";
gt <= "0000000000";
bt <= "0000000000";
elsif(clk'event and clk='1')then
if x>0 and x<213 then -- X方向控制,分为3列,
rt <="0000000000";
bt <="1111111111";
elsif x>=213 and x<426 then
rt <="1111111111";
bt <="0000000000";
else
rt <="1111111111";
bt <="1111111111";
end if;
if y<240 then -- Y方向控制,分为2行
gt <="1111111111";
else
gt <= "0000000000";
end if;
end if;
end process;
-----------------------------------------------------------------------
-----------------------------------------------------------------------
-----------------------------------------------------------------------
process (hst, vst, rt, gt, bt) --色彩输出
begin
if hst = '1' and vst = '1' then
oRed <= rt;
oGreen <= gt;
oBlue <= bt;
else
oRed <= (others => '0');
oGreen <= (others => '0');
oBlue <= (others => '0');
end if;
end process;
end behave;
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