代码搜索：Logic Analyzer

找到约 10,000 项符合「Logic Analyzer」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/146495/5737345

vhd mc8051_siu_.vhd

------------------------------------------------------------------------------- -- -- -- X X XXXXXX XXXXXX
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vhd ports.vhd

--*******************************************************************-- -- Copyright (c) 1999-2001 Evatronix SA -- --****************************************************
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vhd isr.vhd

--*******************************************************************-- -- Copyright (c) 1999-2001 Evatronix SA -- --****************************************************
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www.eeworm.com/read/140841/5779788

vhd ocrcomp.vhd

---------------------------------------------------------------------------- -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2004 GAISLER RESEARCH -- -- This program is free so
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vhd actel_simprims.vhd

---------------------------------------------------------------------------- -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2004 GAISLER RESEARCH -- -- This program is free so
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www.eeworm.com/read/140841/5779832

vhd components.vhd

---------------------------------------------------------------------------- -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2004 GAISLER RESEARCH -- -- This program is free so
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vhd mmu_icache.vhd

---------------------------------------------------------------------------- -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2004 GAISLER RESEARCH -- -- This program is free so
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www.eeworm.com/read/132821/5909168

vhd uart.vhd

---------------------------------------------------------------------------- -- This file is a part of the LEON VHDL model -- Copyright (C) 1999 European Space Agency (ESA) -- -- This library
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vhd numberword.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity numberword is port ( en:in std_logic; clk:in std_logic; load:in std_logic;
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txt 米勒型状态机.txt

-- Mealy State Machine with Registered Outputs -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity mealy1 is port( clk, rst: in
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