isr.vhd

51单片机内核vhdl实现 xilinx平台的

--*******************************************************************--
-- Copyright (c) 1999-2001  Evatronix SA                             --
--*******************************************************************--
-- Please review the terms of the license agreement before using     --
-- this file. If you are not an authorized user, please destroy this --
-- source code file and notify Evatronix SA immediately that you     --
-- inadvertently received an unauthorized copy.                      --
--*******************************************************************--

-----------------------------------------------------------------------
-- Project name         : C8051
-- Project description  : C8051 Microcontroller Unit
--
-- File name            : ISR.VHD
-- File contents        : Entity ISR
--                        Architecture RTL of ISR
-- Purpose              : Interrupt Service Routine Unit
--
-- Destination library  : C8051_LIB
-- Dependencies         : C8051_LIB.Utility
--                        IEEE.STD_LOGIC_1164
--
-- Design Engineer      : D.K. M.B. 
-- Quality Engineer     : M.B.
-- Version              : 3.01.E00
-- Last modification    : 2001-10-01
-----------------------------------------------------------------------

--*******************************************************************--
-- Modifications with respect to Version 3.00.E00:
-- 3.01.E00   :
-- 2001-10-01 : added debugmode input port
-- 2001-10-01 : int_req_write_proc modified in respect to OCI
--*******************************************************************--

library IEEE;
   use IEEE.STD_LOGIC_1164.all;
library C8051_LIB;
   use C8051_LIB.UTILITY.all;

--*******************************************************************--
   entity ISR is
      port (
           -- Control signal inputs
           clk          : in  STD_LOGIC;  -- Global clock input
           rst          : in  STD_LOGIC;  -- Global reset input
           
           -- CPU input signals
           phase        : in  INTEGER range 1 to 6;
           instr        : in  STD_LOGIC_VECTOR(7 downto 0);
           
           -- OCI input signals
           debugmode    : in  STD_LOGIC;
           
           -- Timers/Counters interrupt inputs
           tf0          : in  STD_LOGIC;  -- Timer 0 overflow
           tf1          : in  STD_LOGIC;  -- Timer 1 overflow
           
           -- Serial interface interrupt inputs
           riti         : in  STD_LOGIC;  -- Serial Port interrupt
           
           -- External interrupt inputs
           ie0          : in  STD_LOGIC;  -- External 0 interrupt
           ie1          : in  STD_LOGIC;  -- External 1 interrupt
           
           -- Interrupt return signal
           intret       : in STD_LOGIC;
           
           -- Interrupt acknowledge signal
           intack       : in STD_LOGIC;
           
           -- Interrupt service location
           intvect      : out STD_LOGIC_VECTOR(2 downto 0);
           
           -- Interrupt request signal
           intreq       : out STD_LOGIC;
           
           -- Interrupt acknowledge signals
           t0ack        : out STD_LOGIC;
           t1ack        : out STD_LOGIC;
           int0ack      : out STD_LOGIC;
           int1ack      : out STD_LOGIC;
           
           -- Special function register interface
           sfrdatai     : in  STD_LOGIC_VECTOR(7 downto 0);
           sfrdataisr   : out STD_LOGIC_VECTOR(7 downto 0);
           sfraddr      : in  STD_LOGIC_VECTOR(6 downto 0);
           sfrwe        : in  STD_LOGIC
           );
   end ;

--*******************************************************************--

   architecture RTL of ISR is
   
      -----------------------------------------------------------------
      -- Interrupt service location address
      -----------------------------------------------------------------
      -- address = "0000000000" & intvect & "011"
   
      -----------------------------------------------------------------
      -- Special Function Registers
      -----------------------------------------------------------------
      -- Interrupt enable register
      signal ie         : STD_LOGIC_VECTOR(7 downto 0);
   
      -- Interrupt priority register
      signal ip         : STD_LOGIC_VECTOR(7 downto 0);
   
      -----------------------------------------------------------------
      -- Interrupt mask
      -----------------------------------------------------------------
      signal intmask    : STD_LOGIC_VECTOR(4 downto 0);
   
      -----------------------------------------------------------------
      -- Inerrupt vector locations
      -----------------------------------------------------------------
      signal vect       : STD_LOGIC_VECTOR(2 downto 0);
      signal int_vect   : STD_LOGIC_VECTOR(2 downto 0);
   
      -----------------------------------------------------------------
      -- Priority levels
      -----------------------------------------------------------------
      signal l0         : STD_LOGIC;
      signal l1         : STD_LOGIC;
   
      -----------------------------------------------------------------
      -- Interrupt request level 0 and level 1
      -----------------------------------------------------------------
      signal intreql0   : STD_LOGIC_VECTOR(4 downto 0);
      signal intreql1   : STD_LOGIC_VECTOR(4 downto 0);
      signal intreq_vect: STD_LOGIC_VECTOR(4 downto 0);
   
      -----------------------------------------------------------------
      -- In service register
      -----------------------------------------------------------------
      signal is_reg     : STD_LOGIC_VECTOR(1 downto 0);
      signal is_nxt     : STD_LOGIC_VECTOR(1 downto 0);
   
      -----------------------------------------------------------------
      -- Combinational interrupt request comparator
      -----------------------------------------------------------------
      signal int_req    : STD_LOGIC;
   
   begin
   
   --------------------------------------------------------------------
   -- Inerrupt vector locations register
   --------------------------------------------------------------------
   intvect_drv:
   --------------------------------------------------------------------
      intvect <= int_vect;
   
   --------------------------------------------------------------------
   -- Interrupt enable register 
   --------------------------------------------------------------------
   ie_write_proc:
   --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               ie <= IE_RV;
            else
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               -- Special function register write
               ----------------------------------
               if (sfrwe='1' and sfraddr=IE_ID) then
                  ie <= sfrdatai;
               end if;
            end if;
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   -- Interrupt priority register 
   --------------------------------------------------------------------
   ip_write_proc:
   --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               ip <= IP_RV;
            else
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               -- Special function register write
               ----------------------------------
               if (sfrwe='1' and sfraddr=IP_ID) then
                  ip <= sfrdatai;
               end if;
            end if;
         end if;
      end process;
   
   --------------------------------------------------------------------
   -- interrupt mask
   --------------------------------------------------------------------
   intmask_hand:
   --------------------------------------------------------------------
      intmask <= riti&tf1&ie1&tf0&ie0 and ie(4 downto 0);
   
   --------------------------------------------------------------------
   -- interrupt request level 0
   --------------------------------------------------------------------
   intreql0_hand:
   --------------------------------------------------------------------
      intreql0 <= intmask and not ip(4 downto 0);
   
   --------------------------------------------------------------------
   -- interrupt request level 1
   --------------------------------------------------------------------
   intreql1_hand:
   --------------------------------------------------------------------
      intreql1 <= intmask and ip(4 downto 0);
   
   
   
   --------------------------------------------------------------------
   -- level 0 request
   --------------------------------------------------------------------
   l0_write:
   --------------------------------------------------------------------
      l0 <= ( intreql0(0) or intreql0(1) or intreql0(2) or
              intreql0(3) or intreql0(4)
            );
   
   
   --------------------------------------------------------------------
   -- level 1 request
   --------------------------------------------------------------------
   l1_write:
   --------------------------------------------------------------------
      l1 <= ( intreql1(0) or intreql1(1) or intreql1(2) or
              intreql1(3) or intreql1(4)
            );
   
   
   --------------------------------------------------------------------
   -- interrupt request comparator
   --------------------------------------------------------------------
   int_req_write_proc:
   --------------------------------------------------------------------
      process(clk)
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               int_req <= '0';
            else
            -------------------------------------