numberword.vhd

计数器控制程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity numberword is 
  port
     (
       en:in  std_logic;
       clk:in std_logic;
       load:in std_logic;
       d: in std_logic_vector(11 downto 0);
       co:out std_logic
                   );
end numberword;
architecture behave of numberword is
signal q: std_logic_vector(11 downto 0);
signal ql:std_logic_vector(3 downto 0);
signal qm:std_logic_vector(3 downto 0);
signal qh:std_logic_vector(3 downto 0);
     begin
          process(clk,load)
            begin
               if(load='1') then
                   q<=d ;
                   ql<=q(3 downto 0);
                   qm<=q(7 downto 4);
                   qh<=q(11 downto 8);
                   co<='1';
                 elsif(clk 'event and clk='1') then
                     if(en='0')  then  
                       -- if(ql="0000") then
                          -- ql<="1111";
                         --  if(qm="0000") then 
                           --    qm<="1111";
                           --  if(qh="0000") then
                           --    qh<=q(7 downto 4);
                           --    co<='0';
                            -- else
                            --  qh<=qh-1;
                            --  co<='1';
                            -- end if;
                           --else 
                            --  qm<=qm-1;
                            --  co<='1';
                          --end if;
                      -- else
                        --  ql<=ql-1;
                       --   co<='1';
                      -- end if;
                      if q<="000000000000" then 
                         co<='0';
                      else 
                         co<='1';
                         q<=q-1;
                      end if;
                     end if;
                   end if;         
         end  process;
end behave;