ports.vhd

51单片机内核vhdl实现 xilinx平台的

--*******************************************************************--
-- Copyright (c) 1999-2001  Evatronix SA                             --
--*******************************************************************--
-- Please review the terms of the license agreement before using     --
-- this file. If you are not an authorized user, please destroy this --
-- source code file and notify Evatronix SA immediately that you     --
-- inadvertently received an unauthorized copy.                      --
--*******************************************************************--

-----------------------------------------------------------------------
-- Project name         : C8051
-- Project description  : C8051 Microcontroller Unit
--
-- File name            : PORTS.VHD
-- File contents        : Entity Ports
--                        Architecture RTL of Ports
-- Purpose              : Ports Buffers and Drivers
--
-- Destination library  : C8051_LIB
-- Dependencies         : C8051_LIB.UTILITY
--                        IEEE.STD_LOGIC_1164
--
-- Design Engineer      : M.B. D.K.
-- Quality Engineer     : M.B.
-- Version              : 3.01.E00
-- Last modification    : 2001-10-01
-----------------------------------------------------------------------

--*******************************************************************--
-- Modifications with respect to Version 3.00.E00:
--*******************************************************************--

LIBRARY IEEE;
   USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY c8051_LIB;
   USE c8051_LIB.UTILITY.ALL;

--*******************************************************************--
   entity PORTS is
      port (
           -- Control signals inputs
           clk          : in  STD_LOGIC;  -- Global clock input
           rst          : in  STD_LOGIC;  -- Global reset input
           
           -- Port inputs
           p0i          : in  STD_LOGIC_VECTOR(7 downto 0);
           p1i          : in  STD_LOGIC_VECTOR(7 downto 0);
           p2i          : in  STD_LOGIC_VECTOR(7 downto 0);
           p3i          : in  STD_LOGIC_VECTOR(7 downto 0);
           
           -- Alternate function input
           txd          : in  STD_LOGIC; -- serial async. transmitter
           rxdo         : in  STD_LOGIC; -- serial sync. transmitter
           
           -- CPU control signals
           rmwinstr     : in  STD_LOGIC;  -- Read-Modify-Write Instr.
           
           -- Memory interface
           romdatai     : in  STD_LOGIC_VECTOR( 7 downto 0);
           memdatai     : out STD_LOGIC_VECTOR( 7 downto 0);
           memdatao     : in  STD_LOGIC_VECTOR( 7 downto 0);
           memaddr      : in  STD_LOGIC_VECTOR(15 downto 0);
           memwr        : in  STD_LOGIC;  -- External data memory write
           memrd        : in  STD_LOGIC;  -- External data memory read
           addrdatasel  : in  STD_LOGIC;  -- Address/Data bus select
           memp0acs     : in  STD_LOGIC;  -- Address/Data - port reg.
           memp2acs     : in  STD_LOGIC;  -- Address - port reg. select
           romoe        : in  STD_LOGIC;  -- Int. program memory enabl
           
           -- p2 register
           p2reg        : out STD_LOGIC_VECTOR(7 downto 0);
           
           -- Port outputs
           p0o          : out STD_LOGIC_VECTOR(7 downto 0);
           p1o          : out STD_LOGIC_VECTOR(7 downto 0);
           p2o          : out STD_LOGIC_VECTOR(7 downto 0);
           p3o          : out STD_LOGIC_VECTOR(7 downto 0);
           
           -- Special function register interface
           sfrdatai     : in  STD_LOGIC_VECTOR(7 downto 0);
           sfrdataports : out STD_LOGIC_VECTOR(7 downto 0);
           sfraddr      : in  STD_LOGIC_VECTOR(6 downto 0);
           sfrwe        : in  STD_LOGIC
           );
   end PORTS;

--*******************************************************************--

   architecture RTL of PORTS is
   
      -----------------------------------------------------------------
      -- Special Function Registers
      -----------------------------------------------------------------
      -- Port registers
      signal p0         : STD_LOGIC_VECTOR(7 downto 0);
      signal p1         : STD_LOGIC_VECTOR(7 downto 0);
      signal p2         : STD_LOGIC_VECTOR(7 downto 0);
      signal p3         : STD_LOGIC_VECTOR(7 downto 0);
   
      -----------------------------------------------------------------
      -- Multiplexed Address/Data bus
      -----------------------------------------------------------------
      signal addrdata   : STD_LOGIC_VECTOR(15 downto 0);
   
   begin
   
   --------------------------------------------------------------------
   -- Port alternate functions mapping
   --------------------------------------------------------------------
   -- Port 3 : input      : output
   ------------------------------------
   -- p3(0)  : rxd        : rxdo
   -- p3(1)  :            : txd
   -- p3(2)  : int0       : 
   -- p3(3)  : int1       :
   -- p3(4)  : t0         :
   -- p3(5)  : t1         :
   -- p3(6)  :            : wr
   -- p3(7)  :            : rd
   --------------------------------------------------------------------
   
   --------------------------------------------------------------------
   -- Port 2 register
   --------------------------------------------------------------------
   p2reg_drv:
   --------------------------------------------------------------------
      p2reg <= p2;
   
   
   --------------------------------------------------------------------
   -- Port 0 ouput
   -- Combinational multiplexer
   --------------------------------------------------------------------
   p0_drv:
   --------------------------------------------------------------------
      p0o <= p0 when memp0acs='0' else addrdata(7 downto 0);
   
   
   --------------------------------------------------------------------
   -- Port 1 ouput
   -- Combinational multiplexer
   --------------------------------------------------------------------
   p1_drv:
   --------------------------------------------------------------------
      p1o <=
            (7 => p1(7),
             6 => p1(6),
             5 => p1(5),
             4 => p1(4),
             3 => p1(3),
             2 => p1(2),
             1 => p1(1),
             0 => p1(0)
            );
   
   
   --------------------------------------------------------------------
   -- Port 2 ouput
   -- Combinational multiplexer
   --------------------------------------------------------------------
   p2_drv:
   --------------------------------------------------------------------
      p2o <= p2 when memp2acs='0' else addrdata(15 downto 8);
   
   
   --------------------------------------------------------------------
   -- Port 3 ouput
   -- Combinational multiplexer
   --------------------------------------------------------------------
   p3_drv:
   --------------------------------------------------------------------
      p3o <=
            (7 => p3(7) and not memrd,
             6 => p3(6) and not memwr,
             5 => p3(5),
             4 => p3(4),
             3 => p3(3),
             2 => p3(2),
             1 => p3(1) and txd,
             0 => p3(0) and rxdo
            );
   
   
   --------------------------------------------------------------------
   -- Port registers
   --------------------------------------------------------------------
   ports_write_proc:
   --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               p0(7 downto 0) <= P0_RV;
               p1(7 downto 0) <= P1_RV;
               p2(7 downto 0) <= P2_RV;
               p3(7 downto 0) <= P3_RV;
            else
            
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               -- Special function register write
               ----------------------------------
               if (sfrwe='1' and sfraddr=P0_ID) then
                  p0 <= sfrdatai;
               end if;
               if (sfrwe='1' and sfraddr=P1_ID) then
                  p1 <= sfrdatai;
               end if;
               if (sfrwe='1' and sfraddr=P2_ID) then
                  p2 <= sfrdatai;
               end if;
               if (sfrwe='1' and sfraddr=P3_ID) then
                  p3 <= sfrdatai;
               end if;
            
            end if;
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   -- External memory address bus and data bus multiplexer
   --------------------------------------------------------------------
   addrdata_hand :
   --------------------------------------------------------------------
      addrdata <=
         memaddr(15 downto 8) & memdatao when addrdatasel ='0' else
         memaddr;
   
   
   --------------------------------------------------------------------
   -- Memory interface
   -- Memory input data bus
   -- Combinational multiplexer
   --------------------------------------------------------------------
   memdatai_drv :
   --------------------------------------------------------------------
      memdatai <=
         romdatai when romoe='1' else
         p0i;
   
   
   --------------------------------------------------------------------
   -- Special Function Registers output
   --------------------------------------------------------------------
   sfr_read :
   --------------------------------------------------------------------
      sfrdataports <=
         p0          when sfraddr=P0_ID and rmwinstr='1' else
         p1          when sfraddr=P1_ID and rmwinstr='1' else
         p2          when sfraddr=P2_ID and rmwinstr='1' else
         p3          when sfraddr=P3_ID and rmwinstr='1' else
         p0i         when sfraddr=P0_ID and rmwinstr='0' else
         p1i         when sfraddr=P1_ID and rmwinstr='0' else
         p2i         when sfraddr=P2_ID and rmwinstr='0' else
         p3i         when sfraddr=P3_ID and rmwinstr='0' else
         "--------";
   
   end RTL;
--*******************************************************************--