代码搜索：Logic Analyzer

找到约 10,000 项符合「Logic Analyzer」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/307337/13723955

vhd js.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity js is port (clr, en,clk:in std_logic; sp:out std_logic; qa:out std_logic_vector (3 downto 0);
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www.eeworm.com/read/307337/13723958

vhd jsq.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity jsq is port (clr, en,clk:in std_logic; sp:out std_logic; qa:out std_logic_vector (3 downto 0);
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www.eeworm.com/read/307153/13727461

txt cout10.txt

library ieee; use ieee.std_logic_1164.all; package my_pkg_1 is component cnt10_1 port(clk,clrn,ena,ldn:in std_logic; d:in std_logic_vector(3 downto 0); q:out std_logic_vector(3 down
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www.eeworm.com/read/307021/13732867

vhd subber.vhd

LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY subber IS PORT( a,b,cin : IN STD_LOGIC; --a,b减法器数据输入，cin进位输入信号 s,cout : OUT STD_LOGIC); --s和输出，cout进位输出 END subber; ARCHITECTUR
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www.eeworm.com/read/307021/13732941

vhd csc_top.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY csc_top IS GENERIC (N : INTEGER := 8 ); --输入输出宽度 PORT ( Clock : IN STD_LOGIC; --时钟 ClockEnable : IN ST
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www.eeworm.com/read/306208/13749252

vhd comcoun.vhd

--comcoun.vhd 7 segment com scan counter library ieee ; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity comcoun is port( clk : in std_logic;--synchronouse clock f1k
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www.eeworm.com/read/305986/13755605

txt 米勒型状态机.txt

-- Mealy State Machine with Registered Outputs -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity mealy1 is port( clk, rst: in
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www.eeworm.com/read/305986/13755613

txt 带莫尔_米勒输出的状态机.txt

-- State Machine with Moore and Mealy outputs -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity mealy1 is port( clk, rst: in
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www.eeworm.com/read/305986/13755618

txt 莫尔型状态机2.txt

-- Moore State Machine with Concurrent Output Logic -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity moore1 is port( clk, rst:
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www.eeworm.com/read/305986/13755626

txt 莫尔型状态机1.txt

-- Moore State Machine with explicit state encoding -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity moore2 is port( clk, rst:
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