csc_top.vhd

这是一些经典的vhdl example

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY csc_top IS
    GENERIC (N : INTEGER := 8 );					--输入输出宽度
    PORT ( Clock       : IN  STD_LOGIC;             --时钟
           ClockEnable : IN  STD_LOGIC;             --时钟使能
           Reset       : IN  STD_LOGIC;             --复位
           R           : IN  STD_LOGIC_VECTOR(N-1 DOWNTO 0);  --输入R
           G           : IN  STD_LOGIC_VECTOR(N-1 DOWNTO 0);  --输入G
           B           : IN  STD_LOGIC_VECTOR(N-1 DOWNTO 0);  --输入B
           Y           : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0);  --输出Y
           Cb          : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0);  --输出Cb
           Cr          : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0)   --输出Cr
			);
END csc_top;
ARCHITECTURE RTL OF csc_top IS
--元件主体模块
COMPONENT CSC
GENERIC ( N : INTEGER );
PORT ( Clock       : IN  STD_LOGIC;
       ClockEnable : IN  STD_LOGIC;
       Reset       : IN  STD_LOGIC;
       R           : IN  STD_LOGIC_VECTOR(N-1 DOWNTO 0);
       G           : IN  STD_LOGIC_VECTOR(N-1 DOWNTO 0);
       B           : IN  STD_LOGIC_VECTOR(N-1 DOWNTO 0);
       Y           : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0);
       Cb          : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0);
       Cr          : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0)
	  );
END COMPONENT;
--寄存器锁存的RGB信号
SIGNAL R_sig, G_sig, B_sig               : STD_LOGIC_VECTOR (N-1 DOWNTO 0);
--寄存器锁存输出之前的Y,Cb,Cr信号
SIGNAL Y_sig, Cb_sig, Cr_sig : STD_LOGIC_VECTOR (N-1 DOWNTO 0);
BEGIN
-- 输入锁存
In_Reg: PROCESS (Clock, Reset)
BEGIN
  IF (Reset = '1') THEN
    R_sig <= (OTHERS => '0');
    G_sig <= (OTHERS => '0');
    B_sig <= (OTHERS => '0');
  ELSIF (Clock'event AND Clock = '1') THEN
    IF (ClockEnable = '1') THEN
	   R_sig <= R;
	   G_sig <= G;
	   B_sig <= B;
	 END IF;
  END IF;
END PROCESS;
--输出锁存
Out_Reg: PROCESS (Clock, Reset)
BEGIN
  IF (Reset = '1') THEN
    Y  <= (OTHERS => '0');
    Cb <= (OTHERS => '0');
    Cr <= (OTHERS => '0');
  ELSIF (Clock'event AND Clock = '1') THEN
    IF (ClockEnable = '1') THEN
	   Y  <= Y_sig;
	   Cb <= Cb_sig;
	   Cr <= Cr_sig;
	 END IF;
  END IF;
END PROCESS;
-- 主体模块完成颜色空间转换
CSC_module: csc
  GENERIC MAP ( N => N )
  PORT MAP (
    Clock       => Clock,
    ClockEnable => ClockEnable,
    Reset       => Reset,
    R           => R_sig,
    G           => G_sig,
    B           => B_sig,
    Y           => Y_sig,
    Cb          => Cb_sig,
    Cr          => Cr_sig
	        );
END RTL;