cout10.txt

梁祝乐曲演奏电路设计

library ieee;
use ieee.std_logic_1164.all;
package my_pkg_1 is
 component cnt10_1
port(clk,clrn,ena,ldn:in std_logic;
      d:in std_logic_vector(3 downto 0);
      q:out std_logic_vector(3 downto 0);
    cout:out std_logic);
end component;
component cnt6_1
port(clk,clrn,ena,ldn:in std_logic;
      d:in std_logic_vector(3 downto 0);
      q:out std_logic_vector(3 downto 0);
    cout:out std_logic);
end component;
component and2_1
port(a,b:in std_logic;
       y:out std_logic);
end component;
end my_pkg_1;








library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity and2_1 is
   port (a,b: in std_logic;
           y:out std_logic);
end and2_1;
architecture one of and2_1 is
begin
     y<=a and b;
end one;