代码搜索：Logic Analyzer
找到约 10,000 项符合「Logic Analyzer」的源代码
代码结果 10,000
www.eeworm.com/read/316203/13528488
txt moor1.txt
-- Moore State Machine with explicit state encoding
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore2 is port(
clk, rst:
www.eeworm.com/read/316203/13528496
txt moor2.txt
-- Moore State Machine with Concurrent Output Logic
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore1 is port(
clk, rst:
www.eeworm.com/read/316043/13531511
vhd cpu.vhd
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:00:38 12/17/2007
-- Design Name:
-- Module Name: cpu - Beha
www.eeworm.com/read/315553/13540915
vhd mc8051_ram_.vhd
-------------------------------------------------------------------------------
-- --
-- X X XXXXXX XXXX
www.eeworm.com/read/315109/13551971
vhd reg.vhd
library ieee;
use ieee.std_logic_1164.all;
entity reg is
port
(
clr: in std_logic;
D: in std_logic_vector(15 downto 0);
clock: in std_logic;
write: in std_logic;
sel:
www.eeworm.com/read/314805/13558615
vhdl code.vhdl
library ieee;
library UNISIM;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use UNISIM.VComponents.all;
entity code is
port(
RST: in std_logic;
www.eeworm.com/read/313189/13593340
vhd bianma.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY bianma IS
PORT(d : IN STD_LOGIC_VECTOR(7 downto 0);
e0 : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(2 downto 0);
www.eeworm.com/read/312754/13605434
txt 米勒型状态机.txt
-- Mealy State Machine with Registered Outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
www.eeworm.com/read/312754/13605442
txt 带莫尔_米勒输出的状态机.txt
-- State Machine with Moore and Mealy outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
www.eeworm.com/read/312754/13605447
txt 莫尔型状态机2.txt
-- Moore State Machine with Concurrent Output Logic
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore1 is port(
clk, rst: