bianma.vhd

使用VHDL硬件描述语言边写的奇偶校验程序和3-8译码电路程序

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY bianma IS
		PORT(d      : IN	STD_LOGIC_VECTOR(7 downto 0);
             e0     : IN	STD_LOGIC;
			 q      : OUT	STD_LOGIC_VECTOR(2 downto 0);
             e1,gs  : OUT	STD_LOGIC);
		END bianma;
ARCHITECTURE are OF bianma  IS
	BEGIN
    PROCESS(d,e0)
       BEGIN
        IF(d(7)='0'AND e0='0')THEN
          q<="000";
          gs<='0';
          e1<='1';
        ELSIF(d(6)='0'AND e0='0')THEN
          q<="100";
          gs<='0';
          e1<='1';
        ELSIF(d(5)='0'AND e0='0')THEN
          q<="010";
          gs<='0';
          e1<='1';
        ELSIF(d(4)='0'AND e0='0')THEN
          q<="110";
          gs<='0';
          e1<='1';
        ELSIF(d(3)='0'AND e0='0')THEN
          q<="001";
          gs<='0';
          e1<='1';
        ELSIF(d(2)='0'AND e0='0')THEN
          q<="101";
          gs<='0';
          e1<='1';
        ELSIF(d(1)='0'AND e0='0')THEN
          q<="011";
          gs<='0';
          e1<='1';
        ELSIF(d(0)='0'AND e0='0')THEN
          q<="111";
          gs<='0';
          e1<='1';
        ELSIF(e0='0')THEN
          q<="111";
          gs<='1';
          e1<='0';
        ELSIF(e0='1')THEN
          q<="111";
          gs<='1';
          e1<='1';
     END IF;
 END PROCESS;
END are;