cpu.vhd

32位微处理器的设计

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    23:00:38 12/17/2007 
-- Design Name: 
-- Module Name:    cpu - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use IEEE.std_logic_signed.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity cpu is
    Port ( clk : in  STD_LOGIC;
           data_in : in  signed (31 downto 0);
           reset : in  STD_LOGIC;
           a : out  signed (31 downto 0);
           r : out  STD_LOGIC;
           do : out  signed (31 downto 0);
           wb : out  STD_LOGIC;
           ww : out  STD_LOGIC);
end cpu;

architecture Behavioral of cpu is
	signal xlxn_5:signed(1 downto 0);
	signal xlxn_6:std_logic;
	signal xlxn_12:std_logic;
	signal xlxn_13:std_logic;
	signal xlxn_14:std_logic;
	signal xlxn_15:signed(4 downto 0);
	signal xlxn_16:signed(4 downto 0);
	signal xlxn_17:signed(4 downto 0);
	signal xlxn_18:std_logic;
	signal xlxn_19:std_logic;
	signal xlxn_20:std_logic;
	signal xlxn_22:signed(1 downto 0);
	signal xlxn_23:signed(2 downto 0);
	signal xlxn_25:signed(1 downto 0);
	signal xlxn_27:signed(2 downto 0);
	signal xlxn_28:signed(31 downto 0);
	signal xlxn_29:signed(31 downto 0);
	signal xlxn_30:signed(31 downto 0);
	signal xlxn_31:signed(31 downto 0);
	signal xlxn_33:signed(31 downto 0);
	signal xlxn_34:signed(31 downto 0);
	signal xlxn_35:signed(31 downto 0);
	signal xlxn_36:signed(31 downto 0);
	signal xlxn_37:signed(31 downto 0);
	signal xlxn_39:signed(31 downto 0);
	signal xlxn_40:signed(31 downto 0);
	signal en_ir :std_logic;
	signal instr :signed(31 downto 0);
	
	component alu
	    Port ( alu_c : in  signed(1 downto 0);
           aluin1 : in  signed (31 downto 0);
           aluin2 : in  signed (31 downto 0);
           aluout : out  signed (31 downto 0));
	end component;
	
	component comparer
		port( en_comp:IN std_logic;
			comp_in1:IN signed(31 downto 0);
			comp_in2:IN signed(31 downto 0);
			comp_out:OUT signed(1 downto 0));
	end component;
	
	component cu
	    Port ( clk : in  STD_LOGIC;  
           rst : in  STD_LOGIC;
           compout : in  signed (1 downto 0);  --比较器输出到CU
           r : out  STD_LOGIC;  --读信号
           wb : out  STD_LOGIC; --写字节信号
           ww : out  STD_LOGIC; --写双字信号
           en_r1 : out  STD_LOGIC; --寄存器组一号