代码搜索：Logic Analyzer
找到约 10,000 项符合「Logic Analyzer」的源代码
代码结果 10,000
www.eeworm.com/read/322086/13390214
vhd display.vhd
library ieee;
use ieee.std_logic_1164.all;
entity display is
port
(clock:in std_logic;
flash:in std_logic;
qin:in std_logic_vector(3 downto 0);
display:out std_logic_vector(0 to 7)
);
en
www.eeworm.com/read/321790/13399055
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity altdpram is
generic(
width : integer := 1;
widthad : integer := 1;
numwords : integer := 0;
www.eeworm.com/read/321319/13409092
vhd cnt10.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt10 is
port( clrn,clk,en : in std_logic;
led7s: out std_logic_vector(6 downto 0)
);
end cnt10;
architect
www.eeworm.com/read/320564/13423509
vhd jishu10.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity jishu10 is
port(clk,clr,set:in std_logic;
q:out std_logic_vector(3 downto 0));
end jishu10;
www.eeworm.com/read/319928/13439380
vhd reg.vhd
library ieee;
use ieee.std_logic_1164.all;
entity reg is
port
(
clr: in std_logic;
D: in std_logic_vector(15 downto 0);
clock: in std_logic;
write: in std_logic;
sel:
www.eeworm.com/read/319921/13439520
txt 米勒型状态机.txt
-- Mealy State Machine with Registered Outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
www.eeworm.com/read/319921/13439532
txt 带莫尔_米勒输出的状态机.txt
-- State Machine with Moore and Mealy outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
www.eeworm.com/read/319921/13439535
txt 莫尔型状态机2.txt
-- Moore State Machine with Concurrent Output Logic
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore1 is port(
clk, rst:
www.eeworm.com/read/319921/13439542
txt 莫尔型状态机1.txt
-- Moore State Machine with explicit state encoding
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore2 is port(
clk, rst:
www.eeworm.com/read/318822/13471598
bak add8_3.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
entity add8_3 is
port(
a: in std_logic_vector( 7 downto 0);
b: in std_logic;
cont: in std_logic;
ci: in std_logic_vector(6 downto 0);