display.vhd

自己写的一个VHDL程序

library ieee;
use ieee.std_logic_1164.all;

entity display is
port
(clock:in std_logic;
 flash:in std_logic;
 qin:in std_logic_vector(3 downto 0);
 display:out std_logic_vector(0 to 7)
);
end;

architecture decoder of display is
signal timeout:integer range 0 to 63;
begin
  process(clock)
  begin
    if rising_edge(clock) then
     if flash='0' then
        timeout<=0;
     else
       if timeout=63 then
          timeout<=0;
       else
          timeout<=timeout+1;
       end if;
     end if;
     if timeout<31 then
        case qin is
          when "0000"=>display<="11000000";
          when "0001"=>display<="11111001";
          when "0010"=>display<="10100100";
          when "0011"=>display<="10110000";
          when "0100"=>display<="10011001";
          when "0101"=>display<="10010010";
          when "0110"=>display<="10000010";
          when "0111"=>display<="11111000";
          when "1000"=>display<="10000000";
          when "1001"=>display<="10010000";
          when others=>display<="11111111";
         end case;
       else
          display<="10000000";
       end if;
      end if;
     end process;
 end;