fredevide10.vhd

来自「自己写的一个VHDL程序」· VHDL 代码 · 共 32 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY FreDevide10 IS 
PORT
  (
   Clkin:IN Std_Logic;
   Clkout: OUT Std_Logic
   );
END;

ARCHITECTURE Devider OF FreDevide10 IS
CONSTANT N:Integer:=4;
SIGNAL Counter:Integer RANGE 0 TO N;
SIGNAL     Clk:Std_Logic;
BEGIN
  PROCESS(Clkin)
  BEGIN
    IF rising_edge(Clkin) THEN
       IF Counter=N THEN
          Counter<=0;
          Clk<=Not Clk;
       ELSE 
          Counter<=	Counter+1;
       END IF;
    END IF;
  END PROCESS;
  Clkout<=Clk;
END;