📄 cnt10.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt10 is
port( clrn,clk,en : in std_logic;
led7s: out std_logic_vector(6 downto 0)
);
end cnt10;
architecture a of cnt10 is
signal tmp : std_logic_vector(3 downto 0);
begin
process( clk,clrn,tmp)
begin
if clrn ='0' then tmp<="0000";
elsif (clk'event and clk='1') then
if en='1' then
if tmp<7 then tmp<=tmp + 1;
else tmp<="0000";
end if;
end if;
end if;
case tmp is
when "0001"=> led7s<="0000001";
when "0010"=> led7s<="0000010";
when "0011"=> led7s<="0000100";
when "0100"=> led7s<="0001000";
when "0101"=> led7s<="0010000";
when "0110"=> led7s<="0100000";
when "0111"=> led7s<="1000000";
when others => led7s<="0000000";
end case;
end process;
end a;
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