📄 jishu10.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity jishu10 is
port(clk,clr,set:in std_logic;
q:out std_logic_vector(3 downto 0));
end jishu10;
architecture rtl of jishu10 is
signal count:std_logic_vector(3 downto 0);
begin
q(0)<=count(0);
q(1)<=count(1);
q(2)<=count(2);
q(3)<=count(3);
process(clk,clr)
begin
if(clr='1')then
count<="0000";
elsif(clk'event and clk='1')then
if(set='1')then
if(count="1001")then
count<="0000";
else count<=count+'1';
end if;
end if;
end if;
end process;
end rtl;
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