代码搜索：Logic Analyzer
找到约 10,000 项符合「Logic Analyzer」的源代码
代码结果 10,000
www.eeworm.com/read/325597/13194992
vhd comcoun.vhd
--comcoun.vhd 7 segment com scan counter
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity comcoun is
port(
clk : in std_logic;--synchronouse clock
f1k
www.eeworm.com/read/138605/13228550
vhd comcoun.vhd
--comcoun.vhd 7 segment com scan counter
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity comcoun is
port(
clk : in std_logic;--synchronouse clock
f1k
www.eeworm.com/read/138571/13231239
vhd lineby.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity lineby is
port(
clk:in std_logic;
cp:in std_logic;--复位信号
y:out
www.eeworm.com/read/138571/13231251
vhd lines.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity lines is
port(
clk:in std_logic;
cp:in std_logic;
en0: in s
www.eeworm.com/read/138571/13231633
vhd selectswitch.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity selectswitch is
port(
clk:in std_logic;
key: in std_logic;
en:out s
www.eeworm.com/read/138571/13231676
vhd manualswitch.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity manualswitch is
port(
clk:in std_logic;
key: in std_logic;
en:out s
www.eeworm.com/read/240183/13232350
vhd trace_file.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity trace_file is
Port (flat:in std_logic;
clk:in std_logic;
con
www.eeworm.com/read/240152/13235033
vhd dma_actrl1.1.vhd
--
-- file: dma_actrl.vhd
-- description: DMA (single- and multiword) mode access controller for ATA controller
-- author : Richard Herveille
-- rev.: 1.0 march 9th, 2001
--
-- Host accesses to DMA p
www.eeworm.com/read/324669/13253158
txt 出租车.txt
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Fenpin16 is
port(a,b:in std_logic;
clk6:in std_logic;
clock6:out std_logic);
end;
archi
www.eeworm.com/read/324371/13267029
vhd hour1.vhd
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity hour1 is
Port(
clkh,set,reset:in std_logic;
seth:in std_logic;