hour1.vhd

来自「VHDL写的数字钟」· VHDL 代码 · 共 37 行

Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity hour1 is
 Port(
	  clkh,set,reset:in std_logic;
      seth:in std_logic;           
      hour:buffer std_logic_vector(7 downto 0);         --――时输出端
      Enhour:out std_logic);             -- ――时计时器的进位，用来驱动星期计时器
End;
Architecture a of hour1 is
  Begin
 Process(clkh,reset,set,seth)
	variable h:std_logic_vector(7 downto 0);
  Begin
   If reset='0' then 
		hour<="00000000";
   elsif set='1' then
	  if rising_edge(seth) then
		 if h=23 then
		 	h:="00000000";
		 else
			h:=h+1;
		 end if;
	  end if;
	  hour<=h;            -- ――对时计时器清0
    Elsif clkh'event and clkh='1' then
       if hour=23 then 
		  hour<="00000000";enhour<='1';      -- ――重复计数       
	   else 
		hour<=hour+1;enhour<='0';                  --并产生进位以驱动下一级
       end if;
   end if;
End process;
End;