📄 lines.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity lines is
port(
clk:in std_logic;
cp:in std_logic;
en0: in std_logic_vector(1 downto 0);
L1:out std_logic;
L2:out std_logic;
L3:out std_logic;
L4:out std_logic;
L5:out std_logic;
L6:out std_logic;
L7:out std_logic;
L8:out std_logic;
h1:out std_logic;
h2:out std_logic;
h3:out std_logic;
h4:out std_logic;
h5:out std_logic;
h6:out std_logic;
h7:out std_logic;
h8:out std_logic);
end ;
architecture behavor of lines is
signal b:std_logic_vector(11 downto 0):="000000000000";
signal a:std_logic_vector(2 downto 0);
signal e:std_logic_vector(2 downto 0);
signal c:std_logic_vector(0 to 7);
signal d:std_logic_vector(0 to 7);
begin
process(clk,cp)
begin
if(clk'event and clk='1') then
if(cp ='0')then
b<=b+1;
else
b<="000000000000";
end if;
end if;
end process;
process(clk)
begin
a(0)<=b(6);
a(1)<=b(7);
a(2)<=b(8);
if(clk'event and clk='1') then
if(en0="00")then
if a="000" then c<="10000000";
elsif a="001" then c<="01000000";
elsif a="010" then c<="00100000";
elsif a="011" then c<="00010000";
elsif a="100" then c<="00001000";
elsif a="101" then c<="00000100";
elsif a="110" then c<="00000010";
elsif a="111" then c<="00000001";
end if;
h8<=c(0);
h7<=c(1);
h6<=c(2);
h5<=c(3);
h4<=c(4);
h3<=c(5);
h2<=c(6);
h1<=c(7);
end if;
end if;
end process;
process (clk)
begin
e(0)<=b(9);
e(1)<=b(10);
e(2)<=b(11);
if(clk'event and clk='1')then
if(en0="00")then
if e="000" then d<="01111111";
elsif e="001" then d<="00111111";
elsif e="010" then d<="00011111";
elsif e="011" then d<="00001111";
elsif e="100" then d<="00000111";
elsif e="101" then d<="00000011";
elsif e="110" then d<="00000001";
elsif e="111" then d<="00000000";
end if;
end if;
L8<=d(0);
L7<=d(1);
L6<=d(2);
L5<=d(3);
L4<=d(4);
L3<=d(5);
L2<=d(6);
L1<=d(7);
end if;
end process;
process
end behavor;
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