📄 lineby.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity lineby is
port(
clk:in std_logic;
cp:in std_logic;--复位信号
y:out std_logic_vector(0 to 7));
end lineby;
architecture behavior of lineby is
signal b:std_logic_vector(5 downto 0):="000000";
signal a:std_logic_vector(2 downto 0);
signal e:std_logic_vector(2 downto 0);
signal c:std_logic_vector(0 to 7);
signal d:std_logic_vector(0 to 7);
begin
process(clk,cp)
begin
if(clk'event and clk='1') then
if (cp ='1')then
b<="000000";
else
b<=b+1;
end if;
end if;
end process;
process(clk)
begin
a(0)<=b(0);
a(1)<=b(1);
a(2)<=b(3);
if(clk'event and clk='1') then
if a="000" then c<="10000000";
elsif a="001" then c<="01000000";
elsif a="010" then c<="00100000";
elsif a="011" then c<="00010000";
elsif a="100" then c<="00001000";
elsif a="101" then c<="00000100";
elsif a="110" then c<="00000010";
elsif a="111" then c<="00000001";
end if;
end if;
y<=c;
end process;
end behavior;
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