代码搜索：Logic Analyzer
找到约 10,000 项符合「Logic Analyzer」的源代码
代码结果 10,000
www.eeworm.com/read/330723/12873674
vhd pinball.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Pinball is
port ( clkIn:in std_logic;
scnClk,sysClk:buffer std_logic;
reset:in std_logic;
yesIn,le
www.eeworm.com/read/243259/12952588
txt 新建 文本文档.txt
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity s2 is
port (clk:in std_logic;
clk2:out std_logic:='0'
);
www.eeworm.com/read/140997/13048798
vhd xspfpga.vhd
--------------------------------------------------------------------------------
-- Copyright (c) 2000 by Trenz Electronic.
-- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de
--
www.eeworm.com/read/140872/13055866
vhd bfenpin.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bfenpin is
port(sysclk,clk:in std_logic;
rate: in std_logic_vector(3 downto 0);
bchclk:out std_logi
www.eeworm.com/read/327835/13059792
vhd count24.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY count24 IS
PORT ( clk ,en: IN STD_LOGIC;
cout: OUT STD_LOGIC;
hh,hl: OUT STD_LOGIC_VECTOR(3 DOWNTO 0))
www.eeworm.com/read/327835/13059905
vhd count60.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY count60 IS
PORT ( clk ,en: IN STD_LOGIC;
cout: OUT STD_LOGIC;
hh,hl: OUT STD_LOGIC_VECTOR(3 DOWNTO 0))
www.eeworm.com/read/327832/13060053
vhd mo60.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY mo60 IS
PORT(clk,en:IN STD_LOGIC;
cout:OUT STD_LOGIC;
H:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
www.eeworm.com/read/327832/13060110
vhd count24.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY count24 IS
PORT(clk,en:IN STD_LOGIC;
cout:OUT STD_LOGIC;
H:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
www.eeworm.com/read/327410/13080883
vho mem1.vho
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation
www.eeworm.com/read/327410/13080935
vho memory.vho
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation