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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity s2 is
port (clk:in std_logic;
clk2:out std_logic:='0'
);
end s2;
architecture Behavioral of s2 is
signal discounter:std_logic_vector(27 downto 0);
signal clk1:std_logic:='0';
begin
process(clk)
begin
if (clk='1' and clk'event)then
if(discounter>=X"10D783F")then
discounter<=X"0000000";
clk1<=not clk1;
clk2<=clk1;
else discounter<=discounter+'1';
end if;
end if;
end process;
end Behavioral;
控制灯的程序
library IEEE;
use IEEE.std_logic_1164.all; -- defines std_logic types
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity s2 is
port (
reduce : in STD_LOGIC; -- Active-low switch #3 (left)
jia : in STD_LOGIC; -- Active-low switch #0 (right)
STOP : in STD_LOGIC; -- Active-low switch #2
CLK : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (7 downto 0) := "00000000" -- Active-low LEDs
);
end s2;
architecture Behavioral of s2 is
signal DIR: STD_LOGIC := '0'; -- Left=1, Right=0
signal RUN: STD_LOGIC := '0';
signal q1:STD_LOGIC_VECTOR (3 downto 0):="0000";
signal q2:STD_LOGIC_VECTOR (3 downto 0):="0000";
begin
process (CLK)
begin
if (CLK'event and CLK='1') then -- CLK rising edge
-- DIR register:
if (jia='0') then
DIR <= '0';
elsif (reduce='0') then
DIR <= '1';
end if;
-- RUN register:
if (STOP='0') then
RUN <= '0';
elsif (reduce='0' or jia='0') then
RUN <= '1';
end if;
-- Counter section:
if (RUN='1') then
if (DIR='1') then
q1<=q1+'1';
q2<=q2+'1'; -- Circulate inverted MSB to LSB
else
q1<=q1-'1';
q2<=q2-'1'; -- Circulate inverted LSB to MSB
end if;
end if;
end if;
end process;
q(3 downto 0)<=q1;
q(7 downto 4)<=q2;
end Behavioral;
附录2:#PACE: Start of PACE I/O Pin Assignments
NET "clk" LOC = "c9" ;
NET "jia" LOC = "l13" ;
NET "pout<0>" LOC = "f12" ;
NET "pout<1>" LOC = "e12" ;
NET "pout<2>" LOC = "e11" ;
NET "pout<3>" LOC = "f11" ;
NET "pout<4>" LOC = "f9" ;
NET "pout<5>" LOC = "e9" ;
NET "pout<6>" LOC = "d11" ;
NET "pout<7>" LOC = "c11" ;
NET "re" LOC = "h18" ;
NET "reduce" LOC = "l14" ;
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