count24.vhd

来自「用硬件描述语言(或混合原理图)设计模24计数器模块、4-7显示译码模块、顶层模块」· VHDL 代码 · 共 37 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY count24 IS
PORT(clk,en:IN STD_LOGIC;
       cout:OUT STD_LOGIC;
          H:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
          L:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END count24;

ARCHITECTURE arc OF count24 IS
SIGNAL hq,lq:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
H<=hq;
L<=lq;
 PROCESS(en,clk)
   BEGIN
      IF(clk'EVENT AND clk='1') THEN
        IF(en='1') THEN  
          IF(lq="1001" AND hq<"0010") THEN
          lq<="0000";
          hq<=hq+'1';
          ELSIF(lq="0011" AND hq="0010") THEN
          cout<='1';
          lq<="0000";
          hq<="0000";
          ELSE cout<='0';
               lq<=lq+'1';
          END IF;
        END IF;
      END IF;
 END PROCESS;
END arc;