代码搜索：Logic Analyzer
找到约 10,000 项符合「Logic Analyzer」的源代码
代码结果 10,000
www.eeworm.com/read/196115/8114561
vhd controllogic.vhd
--****************************************************************************************************
-- Control logic for ARM7TDMI-S processor
-- Designed by Ruslan Lepetenok
-- Modified 04.02.20
www.eeworm.com/read/196115/8114601
vhd bbusmultiplexer.vhd
--****************************************************************************************************
-- B bus multiplexer for ARM7TDMI-S processor
-- Designed by Ruslan Lepetenok
-- Modified 04.1
www.eeworm.com/read/196115/8114632
vhd datamux.vhd
--****************************************************************************************************
-- Data multiplexer for ARM memory sybsistem
-- Designed by Ruslan Lepetenok
-- Modified 07.12
www.eeworm.com/read/196012/8118399
vhd gaiiao1.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity gaiiao1 is
port(clk,reset:in std_logic;
q:out std_logic_vector(3 downto 0));
end gaiiao1;
architectur
www.eeworm.com/read/395942/8142383
vhd lock.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity lock is
port( input1: in std_logic_vector(3 downto 0);
input2: in std_logic_vector(3 downto 0);
e
www.eeworm.com/read/247099/12683362
vhd sjb.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sjb is
port(clk,reset:in std_logic;
q:out std_logic_vector(7 downto 0));
end sjb;
architecture sjb_ar
www.eeworm.com/read/247099/12683392
vhd sjb.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sjb is
port(clk,reset:in std_logic;
q:out std_logic_vector(7 downto 0));
end sjb;
architecture sjb_ar
www.eeworm.com/read/333342/12686365
txt pci-t32.txt
--*****************************************************************************
--* *
--* EuCore PCI-T32 - PCI Target Interface Core *
--* (C)2000 MaxLock, Inc. All rights reserved *
--* *
--**
www.eeworm.com/read/145313/12736139
txt 米勒型状态机.txt
-- Mealy State Machine with Registered Outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
www.eeworm.com/read/145313/12736166
txt 带莫尔_米勒输出的状态机.txt
-- State Machine with Moore and Mealy outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in