gaiiao1.vhd

来自「这是正玹实现代码,通过LUT来实现的!!!比其他要简单的多!还有方波,三角波的不」· VHDL 代码 · 共 33 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity gaiiao1 is
  port(clk,reset:in std_logic;
       q:out std_logic_vector(3 downto 0));
end gaiiao1;
architecture gaiiao1_arc of gaiiao1 is
begin 
  process(clk,reset)
  variable tmp:std_logic_vector(3 downto 0);
  variable a:std_logic;
begin
  if reset='1' then
     tmp:="0000";
  elsif clk'event and clk='1' then
     if a='0' then
       tmp:=tmp+1;
          if tmp="1111" then
          a:='1';
          end if;
     end if;    
     if a='1' then
       tmp:=tmp-1;
         if tmp="0000" then
         a:='0';
         end if;
     end if;
  end if;
q<=tmp;
end process;
end gaiiao1_arc;