sjb.vhd

FPGA或CPLD与DAC（DAC0832）

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sjb is
  port(clk,reset:in std_logic;
       q:out std_logic_vector(7 downto 0));
end sjb;
architecture sjb_arc of sjb is
begin
  process(clk,reset)
  variable tmp:std_logic_vector(7 downto 0);
  variable a:std_logic;
begin
  if reset='0' then
     tmp:="00000000";
  elsif clk'event and clk='1' then
     if a='0' then
       if tmp="11111110" then
          tmp:="11111111";
          a:='1';
      else
         tmp:=tmp+1;
      end if;
    else
      if tmp="00000001" then
         tmp:="00000000";
         a:='1';
     else
tmp:=tmp-1;
end if;
   end if;
  end if;
q<=tmp;
end process;
end sjb_arc;