📄 lock.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity lock is
port( input1: in std_logic_vector(3 downto 0);
input2: in std_logic_vector(3 downto 0);
enter: in std_logic;
clk: in std_logic;
func: in std_logic;
speaker: out std_logic;
ledright: out std_logic_vector(3 downto 0);
lederror: out std_logic_vector(3 downto 0);
start: in std_logic;
set: in std_logic;
ring: in std_logic
);
end;
architecture a of lock is
signal sdown:std_logic_vector(7 downto 0);
signal count:std_logic_vector(3 downto 0);
signal count1:std_logic_vector(7 downto 0);
begin
process(clk,enter,input1,input2,func)
variable compare1:std_logic_vector(3 downto 0);
variable compare2:std_logic_vector(3 downto 0);
variable mima1:std_logic_vector(3 downto 0);
variable mima2:std_logic_vector(3 downto 0);
variable flag: std_logic;
begin
if clk'event and clk='1' then
if start='0' then
count<="0000";
speaker<='0';
mima1:="0000";
mima2:="0000";
flag:='0';
compare1:="1111";
compare2:="1111";
count1<="00000000";
sdown<="00000000";
else
if func='1' and enter='1' then
compare1:=input1;
compare2:=input2;
if mima1=compare1 and mima2=compare2 then
ledright<="1111";
lederror<="0000";
flag:='1';
else
ledright<="0000";
lederror<="1111";
count<="1110";
end if;
elsif func='0' and ring='1' and start='1' and sdown<"11111110" then
speaker<=clk;
sdown<=sdown+1;
elsif func='0' and ring='1' and start='1' and sdown>="11111110" then
speaker<='0';
elsif func='0' and ring='0' and start='1' then
sdown<="00000000";
end if;
end if;
end if;
if flag='1' and set='1' and func='1' then
mima1:=input1;
mima2:=input2;
flag:='0';
end if;
if count="1110" and func='1' and count1<"11111110" and start='1' then
speaker<=clk;
count1<=count1+1;
elsif func='1' and count1>="11111110" and start='1' then
speaker<='0';
count<="0000";
count<=count+1;
if count="1110" then
count1<="00000000";
end if;
end if;
end process;
end;
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