代码搜索：Logic Analyzer
找到约 10,000 项符合「Logic Analyzer」的源代码
代码结果 10,000
www.eeworm.com/read/450842/7476035
vhd icache.vhd
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This librar
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vhd fp.vhd
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This librar
www.eeworm.com/read/450837/7476086
vhd usb_new_vsc9_ram_c0.vhd
-- HDLi Version 5.0 IP Bundle 2000.12.15
-- Top HDL file name is usb_new.vhd
-- -----------------------------------------------------------------------------
-- Royal Phili
www.eeworm.com/read/450837/7476087
vhd usb_new_vsc9_ram_c1.vhd
-- HDLi Version 5.0 IP Bundle 2000.12.15
-- Top HDL file name is usb_new.vhd
-- -----------------------------------------------------------------------------
-- Royal Phili
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vhd cnt10.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt10 is
port(clk,rst,en:in std_logic;
cq:out std_logic_vector(3 downto 0);
cout:out std_logic);
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txt cnt10.txt
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt10 is
port(clk,rst,en:in std_logic;
cq:out std_logic_vector(3 downto 0);
cout:out std_logic);
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vhd dpll.vhd
-------数字锁相环------
library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dpll is
port (clk :in std_logic; --clock
rz
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vhd second.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SECOND IS
PORT(CP,EN,Rd:IN STD_LOGIC;
CO: OUT STD_LOGIC;
SH,S
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vhd minute.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY minute IS
PORT(CP,EN,EN2,Rd:IN STD_LOGIC;
CO: OUT STD_LOGIC;
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vhd second.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SECOND IS
PORT(CP,EN,Rd:IN STD_LOGIC;
CO: OUT STD_LOGIC;
SH,S