usb_new_vsc9_ram_c1.vhd

usb rtl code, to fpga or asic

-- HDLi Version 5.0 IP Bundle 2000.12.15
-- Top HDL file name is usb_new.vhd
-- -----------------------------------------------------------------------------
--                          Royal Philips Electronics
-- -----------------------------------------------------------------------------
-- Copyright 2001 by Royal Philips Electronics All rights reserved.
-- 
-- This module is property of Royal Philips Electronics (Philips) and its use
-- is granted to the customer for the sole purpose of implementing in silicon
-- provided by Philips.   This module may only be used in accordance with the
-- provisions of the HDLi License Agreement.
-- 
-- -----------------------------------------------------------------------------
--                           USBFS22 Device Version 1.0
-- -----------------------------------------------------------------------------
-- usb_new/data/USBFS22/RTL/usb_new_vsc9_ram_c1.vhd : RTL VHDL
--
-- Compiled by arkrish on Tue Apr  3 17:23:42 2001
-- -----------------------------------------------------------------------------
-- HDLi Version 5.0 IP Bundle 2000.12.15
-- Top HDL file name is vsc9_ram.vhd
-- -----------------------------------------------------------------------------
--                          Royal Philips Electronics
-- -----------------------------------------------------------------------------
-- Copyright 2001 by Royal Philips Electronics All rights reserved.
-- 
-- This module is property of Royal Philips Electronics (Philips) and its use
-- is granted to the customer for the sole purpose of implementing in silicon
-- provided by Philips.   This module may only be used in accordance with the
-- provisions of the HDLi License Agreement.
-- 
-- -----------------------------------------------------------------------------
--                         BIST SRAM Template Version 2.4
-- -----------------------------------------------------------------------------
-- vsc9_ram_c1.vhd : RTL VHDL
--
-- Compiled by arkrish on Tue Apr  3 11:53:35 2001
-- -----------------------------------------------------------------------------
-- Functional Description:
-- 
-- The BIST circuitry employs the March C+ algorithm for the register file
-- primary port and March C- algorithm for the other ports. Results are 
-- captured via a LFSR. This is a synchronous design using one clock domain 
-- to facilitate scan insertion. The client BIST receives control from the 
-- host BIST via the Client-Host Bus (CHB). The BIST (client) block references 
-- the following modules:
--   top level ____ 
--              |__ signature analyzer
-- When memory self-test is finished, the final signature should be
--   "01011100010100011100111000111001"
-- ---------------------------------------------------------------------------- 
-- Limitations: None known at this time.
-- -----------------------------------------------------------------------------
-- Critical Timing: Hold time of the signals to RAM
-- -----------------------------------------------------------------------------
-- Non-Portable Instantiations: 
-- -----------------------------------------------------------------------------
-- Targeted Technologies: vsc883
-- -----------------------------------------------------------------------------
-- Author: System Technology                         Creation Date: May 1, 1997
-- -----------------------------------------------------------------------------
-- Revision History:
--   1.0   8/97  Initial Release
--   1.2a  4/98  Listed LOUT in the LFSR instantiation (NC in the serial I/F)
-- -----------------------------------------------------------------------------

-- -----------------------------------------------------------------------------
-- Client BIST
-- -----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
----use work.vsc9_ram_lfsr_c1_pkg.all;
library work;
use work.all;

entity vsc9_ram_c1 is
   port ( tck   : in  STD_LOGIC;  -- Test Clock
          chb   : in  STD_LOGIC_VECTOR(15 downto 0);  -- Client Host Bus
          tdi   : in  STD_LOGIC;  -- Test Data Input
          dout  : in  STD_LOGIC_VECTOR(31 downto 0);  -- Memory Data Output
          di    : out STD_LOGIC_VECTOR(31 downto 0);  -- Memory Data Input
          a     : out STD_LOGIC_VECTOR(6 downto 0);  -- Address Bus
          bs    : out STD_LOGIC;  -- Memory Block Enable
          we    : out STD_LOGIC;  -- Memory Write Enable
          tdo   : out STD_LOGIC;  -- Test Data Output
          tbe   : out STD_LOGIC);  -- Test BIST Enable
end vsc9_ram_c1;


architecture RTL of vsc9_ram_c1 is   

   component vsc9_ram_lfsr_c1
      port ( clk : in  STD_LOGIC;
             le  : in  STD_LOGIC;
             csn : in  STD_LOGIC;
             sig : in  STD_LOGIC_VECTOR(31 downto 0);
             se  : in  STD_LOGIC;
             si  : in  STD_LOGIC;
             load : in  STD_LOGIC;
             datain : in  STD_LOGIC_VECTOR(31 downto 0);
             so  : out STD_LOGIC;
             lout : out STD_LOGIC_VECTOR(31 downto 0));

   end component;


-- DEFINE CLIENT PHSICAL PARAs
   CONSTANT CLIENT_MAX_ADDR:  STD_LOGIC_VECTOR(6 downto 0) := "1011111" ;

-- DEFINE THE DATA PATTERN
   CONSTANT pattern00:   STD_LOGIC_VECTOR(31 downto 0) := "00000000000000000000000000000000";  
   CONSTANT pattern00_i: STD_LOGIC_VECTOR(31 downto 0) := "11111111111111111111111111111111";  
   CONSTANT pattern55:   STD_LOGIC_VECTOR(31 downto 0) := "01010101010101010101010101010101";  
   CONSTANT pattern55_i: STD_LOGIC_VECTOR(31 downto 0) := "10101010101010101010101010101010";  
   
-- define the signals in the chb bus     
   signal lfsrcsn: STD_LOGIC;
   signal capture: STD_LOGIC;
   signal load:    STD_LOGIC;
   signal run:     STD_LOGIC;
   signal shift:   STD_LOGIC;
   signal hwe:     STD_LOGIC;
   signal pattern: STD_LOGIC_VECTOR(1 downto 0);
   signal a_alias: STD_LOGIC_VECTOR(6 downto 0);

-- define the internal signals
   signal pre_lfsrso:STD_LOGIC;  -- LFSR scan output
   signal lfsrso:    STD_LOGIC;  -- latched LFSR scan output
   signal datain:    STD_LOGIC_VECTOR(31 downto 0);  -- LFSR data load bus (used in debug mode)
   signal halt:      STD_LOGIC;  -- halt client (synchronous)
   signal lhalt:     STD_LOGIC;  -- latched halt client (synchronous)
   signal dout_alias:      STD_LOGIC_VECTOR(31 downto 0);  -- memory data output
   signal ntck:      STD_LOGIC;
   signal we_alias:  STD_LOGIC;
   signal en_alias:  STD_LOGIC;

begin

   v1: vsc9_ram_lfsr_c1 
   port map (clk    => tck,           -- clock input
             csn    => lfsrcsn,       -- clear synchronous not input
             sig    => dout_alias,    -- signature input bus
             le     => capture,       -- LFSR enable input
             load   => load,          -- load enable input
             datain => datain,        -- data load input bus
             se     => shift,         -- scan select input
             si     => tdi,           -- scan input
             lout   => open,          -- LFSR output bus (NC in the serial I/F)
             so     => pre_lfsrso);   -- scan output

   a <= a_alias;   
   ntck <= not(tck);
               
   datain <= dout_alias;
     
    
-- -----------------------------------------------------------------------
-- Get signal values from the CHB bus
-- -----------------------------------------------------------------------
   tbe     <= chb(0);
   lfsrcsn <= chb(1);
   capture <= chb(2) and not(lhalt);
   load    <= chb(3) and not(lhalt);  
   run     <= chb(4);
   shift   <= chb(5);   
   hwe     <= chb(6);
   pattern <= chb(8 downto 7);
   a_alias <= chb(15 downto 9);


-- -----------------------------------------------------------------------
-- TDO (test data output)
--   It is the data out in the scan path.
-- -----------------------------------------------------------------------
   tdo_logic: process (tdi, lfsrso, shift)
   begin
      if (shift = '0') then
	tdo <= tdi;
      else
        tdo <= lfsrso;
      end if;
   end process;      

   lfsrso_logic: process (ntck)
   begin
     if (ntck = '1' AND ntck'event) then
       lfsrso <= pre_lfsrso;
     end if;
   end process;


-- -----------------------------------------------------------------------
-- LHALT (latched halt)
--   
-- -----------------------------------------------------------------------
   lhalt_logic: process (tck)
   begin
      if (tck = '1' AND tck'event) then
         lhalt <= halt;
      end if;
   end process;      
         

-- -----------------------------------------------------------------------
-- HALT
--    HALT is active when the address is out of the 
--    range, or both read and write port is out of 
--    the range. 
-- -----------------------------------------------------------------------
   halt <= '0';
      
      
-- -----------------------------------------------------------------------
-- DI (memory data input)
--    Every write port can share the same DI bus.
-- -----------------------------------------------------------------------
   di_logic: process (pattern)
   begin
     case pattern is
       when "00"   =>  di <= pattern00;    -- 00 pattern
       when "01"   =>  di <= pattern00_i;  -- FF pattern
       when "10"   =>  di <= pattern55;    -- 55 pattern
       when "11"   =>  di <= pattern55_i;  -- AA pattern
       when others =>    di <= pattern00;
      end case;
   end process;

   dout_alias <= dout;  -- alias

-- -----------------------------------------------------------------------
-- WE (write enable)
-- -----------------------------------------------------------------------
   we_alias <= hwe or halt;
   we   <= not(we_alias);

-- -----------------------------------------------------------------------
-- BS (block select)
-- -----------------------------------------------------------------------
   en_alias <= not(halt) and run;
   bs   <= en_alias;

end RTL; --vsc9_ram_c1.vhd

-- -----------------------------------------------------------------------------
-- VHDL Component Instantiation:
-- -----------------------------------------------------------------------------
-- component vsc9_ram_c1
--    port ( tck    : in STD_LOGIC;
--           chb    : in STD_LOGIC_VECTOR(15 downto 0);
--           tdi    : in STD_LOGIC;
--           dout   : in STD_LOGIC_VECTOR(31 downto 0);
--           di     : out STD_LOGIC_VECTOR(31 downto 0);
--           a      : out STD_LOGIC_VECTOR(6 downto 0);
--           bs     : out STD_LOGIC;
--           we     : out STD_LOGIC;
--           tdo    : out STD_LOGIC;
--           tbe    : out STD_LOGIC);
-- end component;

--
-- u1: vsc9_ram_c1
--    port map ( tck    => ,      -- Test Clock
--               chb    => ,      -- Client Host Bus
--               tdi    => ,      -- Test Data Input
--               dout   => ,      -- Memory Data Output
--               di     => ,      -- Memory Data Input
--               a      => ,      -- Address Bus
--               bs     => ,      -- Memory Block Enable
--               we     => ,      -- Memory Write Enable
--               tdo    => ,      -- Test Data Output
--               tbe    => );     -- Test BIST Enable
-- -----------------------------------------------------------------------------