second.vhd

来自「数字钟的VHDL源程序」· VHDL 代码 · 共 37 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SECOND IS
PORT(CP,EN,Rd:IN STD_LOGIC;
         CO:  OUT STD_LOGIC;
         SH,SL:  OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END SECOND;
ARCHITECTURE STR OF SECOND IS
SIGNAL QN:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
CO<='1' WHEN (QN=X"59" AND EN='1') ELSE '0';
PROCESS(CP,Rd)
BEGIN
		IF (RD='0') THEN
   			QN<=X"00";
  		ELSIF (CP'EVENT AND CP='1') THEN
    		IF (EN='1') THEN
    			IF QN(3 DOWNTO 0)=9 THEN
       				QN(3 DOWNTO 0)<="0000";
       				IF QN(7 DOWNTO 4)=5 THEN
          				QN(7 DOWNTO 4)<="0000";
          			ELSE QN(7 DOWNTO 4)<=QN(7 DOWNTO 4)+1;
       				END IF;
       			ELSE QN(3 DOWNTO 0)<=QN(3 DOWNTO 0)+1;
    			END IF;
    		END IF;
		END IF;
END PROCESS;
SH<=QN(7 DOWNTO 4);
SL<=QN(3 DOWNTO 0);
END STR;