dpll.vhd

全数字fsk调制解调的实现 verilog源码

 
-------数字锁相环------

library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity dpll is
port (clk     :in  std_logic; --clock
      rzcd    :in  std_logic; --code input double edge detection 
      bsyn    :out std_logic);--locked clock     
end dpll;

architecture behav of dpll is

signal bps :std_logic;
signal pre :std_logic_vector(1 downto 0);--edge detection 
signal preset :std_logic_vector(3 downto 0);--count setting 
signal count  :std_logic_vector(3 downto 0);--count 
begin
-----------------------------------------
----------edge detection-----------------
process(clk)
begin
if clk'event and clk='1' then 
    pre(1)<=pre(0);
	pre(0)<=rzcd;
	if(pre="01" or pre="10")
		then bps<='1';
	else
		bps<='0';
	end if;
end if;	
end process;

-----------------------------------------
----------form bit syn-pluse-------------
process(clk)
begin
if clk'event and clk='1' then 
   if (count="0") then count<=preset; else count<=count-1; end if;
   if (count<=11 and count>=4) then bsyn<='1'; else bsyn<='0';end if;
end if;
end process;

-----------------------------------------
--------modify preset value--------------
process(clk)
begin
if clk'event and clk='1' then 
   if(bps='1') then if(count<"0100") then preset<="1001"; end if;
                    if(count>"0100")then preset<="0111";  end if;
                    if(count="0100")then preset<="1000";  end if;
                    --end if;
   end if;
end if;
end process;

-----------------------------------------
-----------------------------------------
end architecture behav;