代码搜索结果
找到约 10,000 项符合
Logic Analyzer 的代码
help.logic.html
Other Notation : Logic
Logic
A logic operation has as inputs a collection of bits, and as an output a single bit. The operation itself is a unique map from the input b
test_logic.v
module test_logic;
reg [31:0] op;
reg clock;
wire [31:0] result;
wire overflow,zero,pn;
arithmetic calca(op,clock,result,overflow,zero,pn);
always begin #25 clock=~clock;end
initial
begin
on_off_logic.vhd
-- **************************************************************
-- File: on_off_logic.vhd
--
-- Purpose: This file implements the flip-flop that detects when
-- on switch is depressed to t
sck_logic.vhd
-- File: sck_logic.vhd
--
-- Created: 8-23-00 ALS
-- This file generates an internal SCK by dividing the system clock as determined by CLKDIV.
-- This internal SCK has a CPHA=1 relationshi
61_logic.vhd
library IEEE;
use IEEE.std_logic_1164.all;
package logic_pack is
function resolve(s : std_ulogic_vector) return std_ulogic;
SUBTYPE logic is resolve std_ulogic;
TYPE logic_vector IS ARRAY
logic_problem.cpp
*****************************************************************************************
//一道QQ上的题目 *
// *
//两个人A，B，数字为2～100之间的共99个自然数。 *
//现找出两个数，把其和告诉A，把其积告诉B。然后 *
//问A知道不
mux_logic.v
vti_encoding:SR|utf8-nl
vti_timelastmodified:TR|13 Jun 2002 17:29:52 -0000
vti_extenderversion:SR|5.0.2.4330
vti_lineageid:SR|{01C41CA6-8897-424C-8C7C-8E2D69BC3F41}
vti_cacheddtm:TX|13 Jun 2002 17
mux_logic.v
module mux_logic (y, select, sig_G, sig_max, sig_a, sig_b);
output y;
input select, sig_G, sig_max, sig_a, sig_b;
assign y = (select == 1) || (sig_G ==1) || (sig_max == 0) ? sig_a : s