on_off_logic.vhd

来自「MP3 for XPLA3 XILINX.CPLD,必须在XILINX的FPGA」· VHDL 代码 · 共 77 行

-- **************************************************************
-- File:  		on_off_logic.vhd
--
-- Purpose: 	This file implements the flip-flop that detects when
--			on switch is depressed to turn off the MP3 portable
--			player. The first switch depression connects the battery
--			to the DC/DC convertor of the MAS3507D and this supplies
--			voltage to the rest of the system. When this switch is 
--			depressed again, this logic sends the ON_OFF signal to the
--			power management logic and the DAC chip is disabled before
--			power is removed. 
--
--			This circuit is basically a toggle flip-flop that detects
--			a rising edge on the PWR switch. The flip-flop is preset to
--			represent the ON state. 
--
-- Created:		11-8-99	ALS
--
-- **************************************************************

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity on_off_logic is
  
  port(
	-- User Interface Signals
	pwr_switch	: in		std_logic;	-- indicates the power switch was depressed

	-- ON/OFF
	on_off	: out 	std_logic;	-- current power status

	-- clock and reset	
      clock		: in		std_logic;	-- 2 MHz system clock
	reset 	: in 		std_logic	-- system reset
);

end on_off_logic;

library IEEE;
use IEEE.std_logic_1164.all;

architecture behave of on_off_logic is

-- ******************** CONSTANT DECLARATIONS ***********************
-- Reset Value
constant RESET_ACTIVE	: 	std_logic := '1';
constant ON_VAL		:	std_logic := '1';
constant OFF_VAL		: 	std_logic := '0';

-- ********************* SIGNAL DECLARATIONS ************************
signal pwr_reg		: 	std_logic ;		-- registered power signal for rising edge detection


begin


-- ************************  On/Off Process ************************
-- This process contains the describes the  flip-flop that maintains
-- the On/Off status

on_off_regs: process (clock, reset)
begin
	if reset = RESET_ACTIVE then
		on_off <= ON_VAL;				-- preset register to show active state
		pwr_reg <= '0';				-- registered version of power switch
	elsif clock'event and clock='1' then

		pwr_reg <= pwr_switch; 			-- register signal from power switch
		if pwr_reg = '0' and pwr_switch = '1' then
			on_off <= OFF_VAL;		-- power switch has been depressed, set On/Off to OFF
		end if;
	end if;
end process;

end behave;