代码搜索：Interface
找到约 10,000 项符合「Interface」的源代码
代码结果 10,000
www.eeworm.com/read/323413/13340928
fse spi_master_interface_bt_top.fse
fsm_encoding {312531251} sequential
fsm_state_encoding {312531251} 00 {00}
fsm_state_encoding {312531251} 01 {01}
fsm_state_encoding {312531251} 10 {10}
fsm_state_encoding {312531251} 11
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srs spi_master_interface_bt_top.srs
#
#
#
# Created by Synplify Verilog HDL Compiler version Compilers 2.6.0, Build 102R from Synplicity, Inc.
# Copyright 1994-1999 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist writte
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srd spi_master_interface_bt_top.srd
f "noname"; #file 0
f "d:\xilinx\spi_t\spi_coolrunner_ver3\clk_gen.v"; #file 1
f "d:\xilinx\spi_t\spi_coolrunner_ver3\counter_4bit.v"; #file 2
f "d:\xilinx\spi_t\spi_coolrunner_ver3\counter_5bit.v"
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tlg spi_master_interface_bt_top.tlg
Selecting top level module spi_master_interface_bt_top
Synthesizing module mcu_interface
@N: CL201 :"D:\XILINX\SPI_T\SPI_COOLRUNNER_VER3\mcu_interface.v":125:3:125:8|Trying to extract state machine
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srm spi_master_interface_bt_top.srm
@E"VRMNFMl;C"RHyVDjCR
"VR8G:\HMDHGb\#H\_0#_bHODFFsMkMCPs_C\sdO_D o3CMPR";yDVHC
R4V8R":H\GDGHM\H#b_#0\bOH_FsFDkCMMsC_PsOd\F0kMCcs_L3H0PR";yDVHC
R.V8R":H\GDGHM\H#b_#0\bOH_FsFDkCMMsC_PsOd\F0kMC6s_L3H0
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ncf spi_master_interface_bt_top.ncf
#
# Constraints generated by Synplify Pro 7.3.5, Build 256R
#
# Period Constraints
#Begin clock constraints
NET "clk" TNM_NET = "clk";
TIMESPEC "TS_clk" = PERIOD "clk" 6.164 ns HIGH 50.00%;
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v spi_master_interface_bt_top.v
module spi_master_interface_bt_top
(clk,reset,tran_done,load_rr,config_done,tr_load,
tx_empty,rec_full,int_n,wr_tr_en,start,miso,mosi,sck,
ss_n,spi_start);
input clk
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cdb nand_interface.(0).cnf.cdb
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qmsg prev_cmp_nand_interface.fit.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
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