spi_master_interface_bt_top.ncf

a verilog prigram for SPI

#
# Constraints generated by Synplify Pro 7.3.5, Build 256R
#

# Period Constraints

#Begin clock constraints
NET "clk" TNM_NET = "clk"; 
TIMESPEC "TS_clk" = PERIOD "clk" 6.164 ns HIGH 50.00%; 
NET "sck_c" TNM_NET = "sck_c"; 
TIMESPEC "TS_sck_c" = PERIOD "sck_c" 3.731 ns HIGH 50.00%; 
#End clock constraints

# Output Constraints
# Input Constraints

# Location Constraints

# End of generated constraints