spi_master_interface_bt_top.v

a verilog prigram for SPI

module spi_master_interface_bt_top
       (clk,reset,tran_done,load_rr,config_done,tr_load,
        tx_empty,rec_full,int_n,wr_tr_en,start,miso,mosi,sck,
        ss_n,spi_start);
        
   input clk,reset;
   output tran_done,load_rr,config_done,tr_load,tx_empty,
          rec_full,int_n,wr_tr_en,start,miso,mosi,sck,
          spi_start;
   output [7:0]ss_n;
   
   wire [31:0]data;
   wire [7:0]spi_data;
   wire [1:0]data_byte,data_byte_int;
   wire rd_n;
   
   spi_master spi(.clk(clk),.reset(reset),.load_rr(load_rr),
                  .config_done(config_done),.tr_load(tr_load),
                  .tx_empty(tx_empty),.rec_full(rec_full),
                  .int_n(int_n),.wr_tr_en(wr_tr_en),.start(start),
                  .miso(miso),.mosi(mosi),.sck(sck),.ss_n(ss_n),
                  .rd_n(rd_n),.data(spi_data));
                  
   spi_master_interface spi_int(.clk(clk),.reset(reset),.spi_start(spi_start),
                                .config_done(config_done),.tr_load(tr_load),
                                .tx_empty(tx_empty),.data_in(data),.data_byte(data_byte),
                                .data_byte_int(data_byte_int),.data(spi_data),
                                .wr_tr_en(wr_tr_en),.start(start),.int_n(int_n),
                                .load_rr(load_rr),.rd_n(rd_n),.tran_done(tran_done));
                        
   spi_master_interface_bt spi_int_bt
   (.clk(clk),.reset(reset),.spi_start(spi_start),.data(data),
    .data_byte(data_byte),.data_byte_int(data_byte_int),
    .tran_done(tran_done),.load_rr(load_rr),.miso(miso),
    .rec_data(spi_data));
    
endmodule