spi_master_interface_bt_top.srd

a verilog prigram for SPI

f "noname"; #file 0
f "d:\xilinx\spi_t\spi_coolrunner_ver3\clk_gen.v"; #file 1
f "d:\xilinx\spi_t\spi_coolrunner_ver3\counter_4bit.v"; #file 2
f "d:\xilinx\spi_t\spi_coolrunner_ver3\counter_5bit.v"; #file 3
f "d:\xilinx\spi_t\spi_coolrunner_ver3\mcu_interface.v"; #file 4
f "d:\xilinx\spi_t\spi_coolrunner_ver3\rec_shift.v"; #file 5
f "d:\xilinx\spi_t\spi_coolrunner_ver3\spi_controller.v"; #file 6
f "d:\xilinx\spi_t\spi_coolrunner_ver3\spi_interface.v"; #file 7
f "d:\xilinx\spi_t\spi_coolrunner_ver3\spi_master.v"; #file 8
f "d:\xilinx\spi_t\spi_coolrunner_ver3\spi_master_interface.v"; #file 9
f "d:\xilinx\spi_t\spi_coolrunner_ver3\spi_master_interface_bt.v"; #file 10
f "d:\xilinx\spi_t\spi_coolrunner_ver3\state_controller.v"; #file 11
f "d:\xilinx\spi_t\spi_coolrunner_ver3\tx_shift.v"; #file 12
f "d:\xilinx\spi_t\spi_coolrunner_ver3\state_controller_top.v"; #file 13
f "d:\xilinx\spi_t\spi_coolrunner_ver3\spi_master_interface_bt_top.v"; #file 14
VNAME 'work.mcu_interface.verilog'; # view id 0
VNAME 'work.tx_shift.verilog'; # view id 1
VNAME 'work.spi_master_interface_bt.verilog'; # view id 2
VNAME 'work.state_controller_top.verilog'; # view id 3
VNAME 'work.state_controller.verilog'; # view id 4
VNAME 'work.counter_5bit.verilog'; # view id 5
VNAME 'work.clk_gen.verilog'; # view id 6
VNAME 'work.rec_shift.verilog'; # view id 7
VNAME 'work.counter_4bit.verilog'; # view id 8
VNAME 'work.spi_controller.verilog'; # view id 9
VNAME 'work.spi_interface.verilog'; # view id 10
VNAME 'work.spi_master.verilog'; # view id 11
VNAME 'work.spi_master_interface_bt_top.verilog'; # view id 12
VNAME 'work.spi_master_interface.verilog'; # view id 13
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