代码搜索：FPGA EDK

找到约 10,000 项符合「FPGA EDK」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/448006/7542015

prm bcd.prm

PROMGEN: Xilinx Prom Generator G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. promgen -w -p mcs -c FF -o g:\girija\fpga\bcd_7seg//bcd -u 0 G:\GIRIJA\FPGA\bcd_7seg\bcd_7seg_cclktemp
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www.eeworm.com/read/445908/7588236

srd emif_com.srd

f "noname"; #file 0 f "d:\eda\synplicity\fpga_81\lib\xilinx\unisim.v"; #file 1 f "d:\eda\synplicity\fpga_81\bin\..\lib\xilinx\unisim.v"; #file 2 f "e:\ise_prj\emif_com\emif_com.v"; #file 3 VNAME '
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www.eeworm.com/read/299656/7840737

xrf ram_256_modelsim.xrf

vendor_name = ModelSim source_file = 1, D:/fpga例子/ram_256/ram_256.vhd source_file = 1, D:/fpga例子/ram_256/ram_256.vwf design_name = ram_256 instance = comp, \we~I\, we, ram_256, 1 instance = comp,
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www.eeworm.com/read/330802/12867718

hier_info mcu_sram_test.hier_info

|mcu_sram_test adstart mcu_fpga_control:inst8.clk clk => sram_control:inst4.clk clk => osc:inst2.clk clk => mfreq:freq8.clk_in wr => mcu_fpga_control:inst8.
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www.eeworm.com/read/142668/12931348

srd not_and.srd

f "noname"; #file 0 f "d:\program files\synplicity\fpga_81\lib\vhd\std.vhd"; #file 1 f "d:\vhdl_exercise\add_full_n\add_full_n.vhd"; #file 2 f "d:\program files\synplicity\fpga_81\lib\vhd\std1164.v
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www.eeworm.com/read/486385/6540731

srd control_mem.srd

f "noname"; #file 0 f "noname"; #file 1 f "d:\program files\synplicity\fpga_81\lib\vhd\std.vhd"; #file 2 f "e:\vhdl\f8051\mc8051_p.vhd"; #file 3 f "d:\program files\synplicity\fpga_81\lib\vhd\std1
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www.eeworm.com/read/486385/6540763

srd mc8051_top.srd

f "noname"; #file 0 f "noname"; #file 1 f "d:\program files\synplicity\fpga_81\lib\vhd\std.vhd"; #file 2 f "e:\vhdl\f8051\mc8051_p.vhd"; #file 3 f "d:\program files\synplicity\fpga_81\lib\vhd\std1
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www.eeworm.com/read/10793/190772

mti uart.cr.mti

F:/EdaOk/project/PeriphDIY/uart/fpga/V0p10/src/rxd.v {2 {vlog -work work -vopt F:/EdaOk/project/PeriphDIY/uart/fpga/V0p10/src/rxd.v Model Technology ModelSim SE vlog 6.2b Compiler 2006.07 Jul 31 2006
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www.eeworm.com/read/17491/732662

mti uart.cr.mti

F:/EdaOk/project/PeriphDIY/uart/fpga/V0p10/src/rxd.v {2 {vlog -work work -vopt F:/EdaOk/project/PeriphDIY/uart/fpga/V0p10/src/rxd.v Model Technology ModelSim SE vlog 6.2b Compiler 2006.07 Jul 31 2006
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www.eeworm.com/read/17670/752774

regkeys

CommandLine E:\FPGA\Xilinx\10.1\ISE\bin\nt\unwrapped\map.exe -ise E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/xapp860.ise -intstyle ise -p xc5vfx130t-ff1738-1 -w -logic_opt off -ol high
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