uart.cr.mti

一个串口的完整FPGA工程

F:/EdaOk/project/PeriphDIY/uart/fpga/V0p10/src/rxd.v {2 {vlog -work work -vopt F:/EdaOk/project/PeriphDIY/uart/fpga/V0p10/src/rxd.v
Model Technology ModelSim SE vlog 6.2b Compiler 2006.07 Jul 31 2006
-- Compiling module rxd
** Warning: F:/EdaOk/project/PeriphDIY/uart/fpga/V0p10/src/rxd.v(266): [RDGN] - Redundant digits in numeric literal.
** Warning: F:/EdaOk/project/PeriphDIY/uart/fpga/V0p10/src/rxd.v(267): [RDGN] - Redundant digits in numeric literal.
** Warning: F:/EdaOk/project/PeriphDIY/uart/fpga/V0p10/src/rxd.v(271): [RDGN] - Redundant digits in numeric literal.
** Warning: F:/EdaOk/project/PeriphDIY/uart/fpga/V0p10/src/rxd.v(273): [RDGN] - Redundant digits in numeric literal.

Top level modules:
	rxd

} {} {}} F:/EdaOk/project/PeriphDIY/uart/fpga/V0p10/src/top.v {1 {vlog -work work -vopt F:/EdaOk/project/PeriphDIY/uart/fpga/V0p10/src/top.v
Model Technology ModelSim SE vlog 6.2b Compiler 2006.07 Jul 31 2006
-- Compiling module top

Top level modules:
	top

} {} {}} F:/EdaOk/project/PeriphDIY/uart/fpga/V0p10/src/divider.v {1 {vlog -work work -vopt F:/EdaOk/project/PeriphDIY/uart/fpga/V0p10/src/divider.v
Model Technology ModelSim SE vlog 6.2b Compiler 2006.07 Jul 31 2006
-- Compiling module divider

Top level modules:
	divider

} {} {}} F:/EdaOk/project/PeriphDIY/uart/fpga/V0p10/src/txd.v {1 {vlog -work work -vopt F:/EdaOk/project/PeriphDIY/uart/fpga/V0p10/src/txd.v
Model Technology ModelSim SE vlog 6.2b Compiler 2006.07 Jul 31 2006
-- Compiling module txd

Top level modules:
	txd

} {} {}} F:/EdaOk/project/PeriphDIY/uart/fpga/V0p10/src/ebi.v {1 {vlog -work work -vopt F:/EdaOk/project/PeriphDIY/uart/fpga/V0p10/src/ebi.v
Model Technology ModelSim SE vlog 6.2b Compiler 2006.07 Jul 31 2006
-- Compiling module ebi

Top level modules:
	ebi

} {} {}} F:/EdaOk/project/PeriphDIY/uart/fpga/V0p10/src/uart.v {2 {vlog -work work -vopt F:/EdaOk/project/PeriphDIY/uart/fpga/V0p10/src/uart.v
Model Technology ModelSim SE vlog 6.2b Compiler 2006.07 Jul 31 2006
-- Compiling module uart
** Warning: F:/EdaOk/project/PeriphDIY/uart/fpga/V0p10/src/uart.v(58): [RDGN] - Redundant digits in numeric literal.
** Warning: F:/EdaOk/project/PeriphDIY/uart/fpga/V0p10/src/uart.v(59): [RDGN] - Redundant digits in numeric literal.
** Warning: F:/EdaOk/project/PeriphDIY/uart/fpga/V0p10/src/uart.v(60): [RDGN] - Redundant digits in numeric literal.
** Warning: F:/EdaOk/project/PeriphDIY/uart/fpga/V0p10/src/uart.v(61): [RDGN] - Redundant digits in numeric literal.
** Warning: F:/EdaOk/project/PeriphDIY/uart/fpga/V0p10/src/uart.v(62): [RDGN] - Redundant digits in numeric literal.
** Warning: F:/EdaOk/project/PeriphDIY/uart/fpga/V0p10/src/uart.v(63): [RDGN] - Redundant digits in numeric literal.
** Warning: F:/EdaOk/project/PeriphDIY/uart/fpga/V0p10/src/uart.v(64): [RDGN] - Redundant digits in numeric literal.
** Warning: F:/EdaOk/project/PeriphDIY/uart/fpga/V0p10/src/uart.v(65): [RDGN] - Redundant digits in numeric literal.

Top level modules:
	uart

} {} {}} F:/EdaOk/project/PeriphDIY/uart/fpga/V0p10/testbench/top_tb.v {1 {vlog -work work -vopt F:/EdaOk/project/PeriphDIY/uart/fpga/V0p10/testbench/top_tb.v
Model Technology ModelSim SE vlog 6.2b Compiler 2006.07 Jul 31 2006
-- Compiling module top_tb

Top level modules:
	top_tb

} {} {}}