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FPGA 的代码
generic_spram.v
`include "timescale.v"
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
`define VENDOR_FPGA
module generic_spram(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, ad
state_moor_mealy.txt
-- State Machine with Moore and Mealy outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
米勒型状态机.txt
-- Mealy State Machine with Registered Outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
cam_top.vhd
--
-- Module: CAM_Top / Top Level
-- Design: CAM_Top
-- VHDL code: Hierarchical wrapper
-- Instantiate CAM_generic_8s (depth variable by 16x8bits word)
--
-- Synthesis Synopsys FPGA Express v
init_8_ram16x1s.v
//
// Module: INIT_8_RAM16x1s
// Design: CAM_Top
// Verilog code: RTL / Combinatorial
//
// Synthesis_tool Synopsys FPGA Express ver. 3.3
// Enable Synthesis Option: Verilog Pre-pro
init_ramb4_s1_s16.v
//
// Module: INIT_RAMB4_S1_S16
// Design: CAM_Top
// Verilog code: RTL / Combinatorial
//
// Synthesis_tool Synopsys FPGA Express ver. 3.3
// Enable Synthesis Option: Verilog Pre-p
main.c~
#include
#include "Omap30.h"
#include "Omap30_armwdg.h"
#include "..\header\armperipherals.h"
#include "..\header\FPGA_peripherals.h"
#include "swi.h"
//int SetupGPIOHandler(unsigned
main.c
#include
#include "Omap30.h"
#include "Omap30_armwdg.h"
#include "..\header\armperipherals.h"
#include "..\header\FPGA_peripherals.h"
#include "swi.h"
//int SetupGPIOHandler(unsigned
state_moor_mealy.txt
-- State Machine with Moore and Mealy outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
米勒型状态机.txt
-- Mealy State Machine with Registered Outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in