init_ramb4_s1_s16.v

Using Block RAM for High-Performance Read.Write Cams

//
// Module: 	INIT_RAMB4_S1_S16
// Design: 	CAM_Top
// Verilog code:	RTL / Combinatorial
//
// Synthesis_tool	Synopsys FPGA Express ver. 3.3 
//	 	        Enable Synthesis Option: Verilog Pre-procesor
//
// Description: Basic building block of a CAM using Select BlockRAM
//		16 words depth x 8 bits width
//		Instantiation RAMB4_S1_S16
//		Initialization of RAMB4: attributes to constraint PAR and simulation
//
//
// Device: 	VIRTEX Families
//
// Created by: Jean-Louis BRELET / XILINX - VIRTEX Applications
// Converted to Verilog: Maria George - VIRTEX Applications
// Date: December 8, 1999
// Version: 1.0
//
// History: 
// 	1. 12/08/99 MG - Translated to Verilog
//
//   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
//                WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
//                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
//                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
//
//  Copyright (c) 1999 Xilinx, Inc.  All rights reserved.
//////////////////////////////////////////////////////////////////////////////////////////////////////-

module INIT_RAMB4_S1_S16 (DIA, ENA, ENB, WEA, RSTB, CLK, ADDRA, ADDRB, DOB);

input DIA, ENA, ENB, WEA, RSTB, CLK;
input [11:0] ADDRA;
input [7:0] ADDRB;
output [15:0] DOB;

// Internal Signal Declarations

wire [0:0] DIA_TMP;
wire [15:0] BUS16_GND;
wire GND;


// reg [15:0] DOB;

//synopsys dc_script_begin

//set_attribute RAMB4 INIT_00
"0000000000000000000000000000000000000000000000000000000000000000" -type string

//set_attribute RAMB4 INIT_01
"0000000000000000000000000000000000000000000000000000000000000000" -type string

//set_attribute RAMB4 INIT_02
"0000000000000000000000000000000000000000000000000000000000000000" -type string

//set_attribute RAMB4 INIT_03
"0000000000000000000000000000000000000000000000000000000000000000" -type string

//set_attribute RAMB4 INIT_04
"0000000000000000000000000000000000000000000000000000000000000000" -type string

//set_attribute RAMB4 INIT_05
"0000000000000000000000000000000000000000000000000000000000000000" -type string

//set_attribute RAMB4 INIT_06
"0000000000000000000000000000000000000000000000000000000000000000" -type string

//set_attribute RAMB4 INIT_07
"0000000000000000000000000000000000000000000000000000000000000000" -type string

//set_attribute RAMB4 INIT_08
"0000000000000000000000000000000000000000000000000000000000000000" -type string

//set_attribute RAMB4 INIT_09
"0000000000000000000000000000000000000000000000000000000000000000" -type string

//set_attribute RAMB4 INIT_0A
"0000000000000000000000000000000000000000000000000000000000000000" -type string

//set_attribute RAMB4 INIT_0B
"0000000000000000000000000000000000000000000000000000000000000000" -type string

//set_attribute RAMB4 INIT_0C
"0000000000000000000000000000000000000000000000000000000000000000" -type string

//set_attribute RAMB4 INIT_0D
"0000000000000000000000000000000000000000000000000000000000000000" -type string

//set_attribute RAMB4 INIT_0E
"0000000000000000000000000000000000000000000000000000000000000000" -type string

//set_attribute RAMB4 INIT_0F
"0000000000000000000000000000000000000000000000000000000000000000" -type string

//synopsys dc_script_end

assign GND = 1'b0;
assign BUS16_GND = 16'h0000;
assign DIA_TMP[0] = DIA;

RAMB4_S1_S16 RAMB4 (.DIA(DIA_TMP), .DIB(BUS16_GND), .ENA(ENA), .ENB(ENB), .WEA(WEA),
                    .WEB(GND), .RSTA(GND), .RSTB(RSTB), .CLKA(CLK), .CLKB(CLK),
                    .ADDRA(ADDRA), .ADDRB(ADDRB), .DOB(DOB));
                    

//synopsys translate_off

defparam RAMB4.INIT_00 =
256'h0000000000000000000000000000000000000000000000000000000000000000;

defparam RAMB4.INIT_01 =
256'h0000000000000000000000000000000000000000000000000000000000000000;

defparam RAMB4.INIT_02 =
256'h0000000000000000000000000000000000000000000000000000000000000000;

defparam RAMB4.INIT_03 =
256'h0000000000000000000000000000000000000000000000000000000000000000;

defparam RAMB4.INIT_04 =
256'h0000000000000000000000000000000000000000000000000000000000000000;

defparam RAMB4.INIT_05 =
256'h0000000000000000000000000000000000000000000000000000000000000000;

defparam RAMB4.INIT_06 =
256'h0000000000000000000000000000000000000000000000000000000000000000;

defparam RAMB4.INIT_07 =
256'h0000000000000000000000000000000000000000000000000000000000000000;

defparam RAMB4.INIT_08 =
256'h0000000000000000000000000000000000000000000000000000000000000000;

defparam RAMB4.INIT_09 =
256'h0000000000000000000000000000000000000000000000000000000000000000;

defparam RAMB4.INIT_0A =
256'h0000000000000000000000000000000000000000000000000000000000000000;

defparam RAMB4.INIT_0B =
256'h0000000000000000000000000000000000000000000000000000000000000000;

defparam RAMB4.INIT_0C =
256'h0000000000000000000000000000000000000000000000000000000000000000;

defparam RAMB4.INIT_0D =
256'h0000000000000000000000000000000000000000000000000000000000000000;

defparam RAMB4.INIT_0E =
256'h0000000000000000000000000000000000000000000000000000000000000000;

defparam RAMB4.INIT_0F =
256'h0000000000000000000000000000000000000000000000000000000000000000;

//synopsys translate_on

endmodule