cam_top.vhd

Using Block RAM for High-Performance Read.Write Cams

--
-- Module: 	CAM_Top / Top Level
-- Design: 	CAM_Top
-- VHDL code:	Hierarchical wrapper
--		Instantiate CAM_generic_8s (depth variable by 16x8bits word)
--
-- Synthesis	Synopsys FPGA Express ver. 3.2 - Option = Preserve Hierarchy
--		Use of "pragma synthesis_off/on" and attributes
--
-- Description: 	Instantiate a CAM implementation
--		Registered inputs and outputs (CAM internal timing analysis)
--
-- Device: 	VIRTEX Family (VIRTEX & VIRTEX-E)
--
-- Created by: Jean-Louis BRELET / XILINX - VIRTEX Applications
-- Date: July 29, 1999
-- Version: 1.0
--
-- History: 
-- 	1. JLB-09/13/99 GLOBAL_RST active High
--	2. JLB-09/24/99 Remove  WRITE_ENABLE & MATCH_RST input registers
--
--   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
--                WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
--                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
--                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
--  Copyright (c) 1999 Xilinx, Inc.  All rights reserved.
-------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

-- Syntax for Synopsys FPGA Express
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on

entity CAM_Top is -- Convention: All I_XXX are inputs to be registered, O_XXX are registered outputs
    generic (
        addr_width 		: integer := 5; -- CAM 32 words / 6; -- CAM 64 words / 7; -- CAM 128 words / 8; -- CAM 256 words
        nb_cam16x8s		: integer := 2 -- CAM 2 x16 = 32 / 4 -- CAM 4x16 = 64 / 8 -- CAM 8x16 = 128 / 16 -- CAM 16x16 = 256   
    );
    port (
        I_DATA_IN		: in std_logic_vector (7 downto 0); -- Data to compare or to write
        I_ADDR		: in std_logic_vector (addr_width-1 downto 0); -- Address when write ONLY
        WRITE_ENABLE	: in std_logic; -- Write Enable if High (2 clock cycles)
        I_CLK		: in std_logic;
        GLOBAL_RST		: in std_logic; -- Global Asynchronous Reset (GSR ressource)
        I_MATCH_ENABLE	: in std_logic; -- Enable to find a match, otherwise No change on MATCH bus.
        MATCH_RST		: in std_logic; -- If '0' the MATCH bus outputs "0000000000000000" when MATCH_ENABLE = '1'
        O_MATCH_ADDR	: out std_logic_vector (addr_width-1 downto 0); -- Match address found
        O_MATCH_OK		: out std_logic -- '1' if MATCH found
--        O_ADDR_VALID	: out std_logic -- '1' when O_MATCH_ADDR is valid
    );
end CAM_Top;

architecture CAM_Top_arch of CAM_Top is
--
-- Components Declarations:
component CAM_generic_8s
    	generic (
       	addr_width 	: integer; 
	nb_cam16x8s	: integer
   	);
    port (
        DATA_IN		: in std_logic_vector (7 downto 0);	
        ADDR		: in std_logic_vector (addr_width-1 downto 0);
        WRITE_ENABLE	: in std_logic;	
        CLK			: in std_logic;
        MATCH_ENABLE	: in std_logic;		
        MATCH_RST		: in std_logic;
        GLOBAL_RST		: in std_logic;		
        R_MATCH_ADDR	: out std_logic_vector (addr_width-1 downto 0);
        R_MATCH_OK		: out std_logic
--       ADDR_VALID		: out std_logic
    );
end component;
--
component BUFGDLL
	port (
	I	: in std_logic;
	O	: out std_logic
	);
end component;
--
-- Signal Declarations:
signal DATA_IN 		: std_logic_vector(7 downto 0);
signal ADDR 		: std_logic_vector(addr_width-1 downto 0);
signal MATCH_ENABLE	: std_logic;
signal CLK 		: std_logic;
signal MATCH_ADDR 	: std_logic_vector(addr_width-1 downto 0);
signal MATCH_OK 		: std_logic;
-- signal ADDR_VALID : std_logic;
-- signal VCC : std_logic;
-- signal GND : std_logic;
--
begin
-- VCC <= '1';
-- GND <= '0';
--
-- Instantiate the DLL
BUF_DLL: BUFGDLL
	port map (
	I => I_CLK,
	O => CLK
	);
--
-- Registered inputs and outputs
REGISTERED_IO: process (GLOBAL_RST, CLK)
begin
	if ( GLOBAL_RST = '1') then
		DATA_IN <= (others => '0');
		ADDR <= (others => '0');
		MATCH_ENABLE <= '0';
		O_MATCH_ADDR <= (others => '0');
		O_MATCH_OK <= '0';
--		O_ADDR_VALID <= '0';
	else
		if (CLK'event and CLK = '1') then 
			DATA_IN <= I_DATA_IN;
			ADDR <= I_ADDR;
			MATCH_ENABLE <= I_MATCH_ENABLE;
			O_MATCH_ADDR <= MATCH_ADDR;
			O_MATCH_OK <= MATCH_OK;
--			O_ADDR_VALID <= ADDR_VALID;
		end if;
	end if;
end process REGISTERED_IO;

-- Instantiate CAM
CAM_generic_8s_1: CAM_generic_8s
	generic map ( 
	addr_width => addr_width,
        	nb_cam16x8s=> nb_cam16x8s
   	 )
	port map (
	DATA_IN => DATA_IN,
        	ADDR => ADDR,
        	WRITE_ENABLE => WRITE_ENABLE,	
         	CLK => CLK,
        	MATCH_ENABLE => MATCH_ENABLE,	
        	MATCH_RST => MATCH_RST,
        	GLOBAL_RST => GLOBAL_RST,		
        	R_MATCH_ADDR => MATCH_ADDR,
        	R_MATCH_OK => MATCH_OK
--        	ADDR_VALID => ADDR_VALID
	);
--
end CAM_Top_arch;