init_8_ram16x1s.v

Using Block RAM for High-Performance Read.Write Cams

//
// Module: 	INIT_8_RAM16x1s
// Design: 	CAM_Top
// Verilog code:	RTL / Combinatorial
//
// Synthesis_tool	Synopsys FPGA Express ver. 3.3 
//	 	        Enable Synthesis Option: Verilog Pre-procesor
//
// Description: Basic building block of a CAM using Select BlockRAM & Select RAM
//		Instantiate 8 RAM16x1s_1 for ERASE operation
//		Initialization of RAM16x1s: attributes to constraint PAR and simulation
//
//
//
// Device: 	VIRTEX Families
//
// Created by: Jean-Louis BRELET / XILINX - VIRTEX Applications
// Converted to Verilog: Maria George - VIRTEX Applications
// Date: December 8, 1999
// Version: 1.0
//
// History: 
// 	1. 12/08/99 MG - Translated to Verilog
//
//   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
//                WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
//                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
//                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
//
//  Copyright (c) 1999 Xilinx, Inc.  All rights reserved.
//////////////////////////////////////////////////////////////////////////////////////////////////////-

module INIT_8_RAM16x1s (DATA_IN, 
                        ADDR,          // Used by erase/write operation only
                        WRITE_RAM,     // If '1' DATA_IN is WRITE in the RAM_B4
                        CLK,
                        DATA_WRITE);
                        
                        
input CLK, WRITE_RAM;
input [7:0] DATA_IN;
input [3:0] ADDR;
output [7:0] DATA_WRITE;

//reg [7:0] DATA_WRITE;

//synopsys dc_script_begin
//set_attribute RAM_ERASE_0 INIT
"0000"
//set_attribute RAM_ERASE_1 INIT
"0000"
//set_attribute RAM_ERASE_2 INIT
"0000"
//set_attribute RAM_ERASE_3 INIT
"0000"
//set_attribute RAM_ERASE_4 INIT
"0000"
//set_attribute RAM_ERASE_5 INIT
"0000"
//set_attribute RAM_ERASE_6 INIT
"0000"
//set_attribute RAM_ERASE_7 INIT
"0000"
//synopsys dc_script_end


RAM16x1s_1 RAM_ERASE_0 (.WE(WRITE_RAM), .WCLK(CLK), .D(DATA_IN[0]), 
                                .A0(ADDR[0]), .A1(ADDR[1]), .A2(ADDR[2]),
                                .A3(ADDR[3]), .O(DATA_WRITE[0]));
                                

RAM16x1s_1 RAM_ERASE_1 (.WE(WRITE_RAM), .WCLK(CLK), .D(DATA_IN[1]), 
                                .A0(ADDR[0]), .A1(ADDR[1]), .A2(ADDR[2]),
                                .A3(ADDR[3]), .O(DATA_WRITE[1])); 
                                

RAM16x1s_1 RAM_ERASE_2 (.WE(WRITE_RAM), .WCLK(CLK), .D(DATA_IN[2]), 
                                .A0(ADDR[0]), .A1(ADDR[1]), .A2(ADDR[2]),
                                .A3(ADDR[3]), .O(DATA_WRITE[2]));  

RAM16x1s_1 RAM_ERASE_3 (.WE(WRITE_RAM), .WCLK(CLK), .D(DATA_IN[3]), 
                                .A0(ADDR[0]), .A1(ADDR[1]), .A2(ADDR[2]),
                                .A3(ADDR[3]), .O(DATA_WRITE[3]));
                        
RAM16x1s_1 RAM_ERASE_4 (.WE(WRITE_RAM), .WCLK(CLK), .D(DATA_IN[4]), 
                                .A0(ADDR[0]), .A1(ADDR[1]), .A2(ADDR[2]),
                                .A3(ADDR[3]), .O(DATA_WRITE[4]));
                                
RAM16x1s_1 RAM_ERASE_5 (.WE(WRITE_RAM), .WCLK(CLK), .D(DATA_IN[5]), 
                                .A0(ADDR[0]), .A1(ADDR[1]), .A2(ADDR[2]),
                                .A3(ADDR[3]), .O(DATA_WRITE[5]));
                                
RAM16x1s_1 RAM_ERASE_6 (.WE(WRITE_RAM), .WCLK(CLK), .D(DATA_IN[6]), 
                                .A0(ADDR[0]), .A1(ADDR[1]), .A2(ADDR[2]),
                                .A3(ADDR[3]), .O(DATA_WRITE[6]));
                                
RAM16x1s_1 RAM_ERASE_7 (.WE(WRITE_RAM), .WCLK(CLK), .D(DATA_IN[7]), 
                                .A0(ADDR[0]), .A1(ADDR[1]), .A2(ADDR[2]),
                                .A3(ADDR[3]), .O(DATA_WRITE[7]));
                                
//synopsys translate_off

defparam RAM_ERASE_0.INIT = 16'h0000;

defparam RAM_ERASE_1.INIT = 16'h0000;

defparam RAM_ERASE_2.INIT = 16'h0000;

defparam RAM_ERASE_3.INIT = 16'h0000;

defparam RAM_ERASE_4.INIT = 16'h0000;

defparam RAM_ERASE_5.INIT = 16'h0000;

defparam RAM_ERASE_6.INIT = 16'h0000;

defparam RAM_ERASE_7.INIT = 16'h0000;

//synopsys translate_on
                                
endmodule // INIT_8_RAM16x1s