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t_compact.vhw
-- D:\FPGA\仿真\DIVIDER
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Mon May 29 11:41:17 2006
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Test Bench
fifo.txt
-- A First-in First-out Memory
-- a first-in first out memory, uses a synchronising clock
-- generics allow fifos of different sizes to be instantiated
-- download from: www.fpga.com.cn & www.pld.c
fifo.txt
-- A First-in First-out Memory
-- a first-in first out memory, uses a synchronising clock
-- generics allow fifos of different sizes to be instantiated
-- download from: www.fpga.com.cn & www.pld.c
fifo存储器举例：(注3).txt
-- A First-in First-out Memory
-- a first-in first out memory, uses a synchronising clock
-- generics allow fifos of different sizes to be instantiated
-- download from: www.fpga.com.cn & www.pld.c
display.v
`timescale 1ns/10ps
`define D #1
//===FPGA Training project==//
//==Seven segment display block==//
//==Marshall,2006.04.05==//
module Display(
/*input*/Reset,Clk128Hz,HourH,HourL,MinH,Mi
init_ramb4_s1_s16.vhd
--
-- Module: INIT_RAMB4_S1_S16
-- Design: CAM_Top
-- VHDL code: VIRTEX primitives instantiation
--
-- Synthesis Synopsys FPGA Express ver. 3.2
-- Use of "pragma synthesis_off/on" and attrib
init_8_ram16x1s.vhd
--
-- Module: INIT_8_RAM16x1s
-- Design: CAM_Top
-- VHDL code: VIRTEX primitives instantiation
--
-- Synthesis Synopsys FPGA Express ver. 3.2
-- Use of "pragma synthesis_off/on" and attribut
fifo
-- A First-in First-out Memory
-- a first-in first out memory, uses a synchronising clock
-- generics allow fifos of different sizes to be instantiated
-- download from: www.fpga.com.cn & www.pld.c
fifo.txt
-- A First-in First-out Memory
-- a first-in first out memory, uses a synchronising clock
-- generics allow fifos of different sizes to be instantiated
-- download from: www.fpga.com.cn & www.pld.c
fifo存储器举例：(注3).txt
-- A First-in First-out Memory
-- a first-in first out memory, uses a synchronising clock
-- generics allow fifos of different sizes to be instantiated
-- download from: www.fpga.com.cn & www.pld.c