init_ramb4_s1_s16.vhd

Using Block RAM for High-Performance Read.Write Cams

--
-- Module: 	INIT_RAMB4_S1_S16
-- Design: 	CAM_Top
-- VHDL code:	VIRTEX primitives instantiation
--
-- Synthesis	Synopsys FPGA Express ver. 3.2 
--		Use of "pragma synthesis_off/on" and attributes
--
-- Description: Basic building block of a CAM using Select BlockRAM
--		16 words depth x 8 bits width
--		Instantiation RAMB4_S1_S16
--		Initialization of RAMB4: attributes to constraint PAR and simulation
--
-- Device: 	VIRTEX Family (VIRTEX & VIRTEX-E)
--		1 RAMB4 
--
-- Created by: Jean-Louis BRELET / XILINX - VIRTEX Applications
-- Date: July 29, 1999
-- Version: 1.0
--
-- History: 
-- 	1. 
--
--   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
--                WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
--                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
--                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
--  Copyright (c) 1999 Xilinx, Inc.  All rights reserved.
-------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

-- Syntax for Synopsys FPGA Express
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on


entity INIT_RAMB4_S1_S16 is
    port (
	DIA    	: in std_logic;
	ENA    	: in std_logic;
	ENB    	: in std_logic;
	WEA    	: in std_logic;
	RSTB   	: in std_logic;
	CLK   	: in std_logic; -- Same clock on ports A & B
	ADDRA  	: in std_logic_vector (11 downto 0);
	ADDRB  	: in std_logic_vector (7 downto 0);
	DOB    	: out std_logic_vector (15 downto 0)
	); -- unused input ports are tied to GND
end INIT_RAMB4_S1_S16;

architecture INIT_RAMB4_S1_S16_arch of INIT_RAMB4_S1_S16 is
--
-- Components Declarations:
--	
component RAMB4_S1_S16 
-- RAM initialization of RTL simulation 
-- Syntax for Synopsys FPGA Express
-- pragma synthesis_off
generic( 
       INIT_00 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_01 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_02 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_03 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_04 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_05 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_06 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_07 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_08 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_09 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_0A : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_0B : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_0C : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_0D : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_0E : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_0F : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"
  );
-- pragma synthesis_on
    port (
	DIA    	: in std_logic_vector(0 downto 0);
	DIB    	: in std_logic_vector (15 downto 0);
	ENA    	: in std_logic;
	ENB    	: in std_logic;
	WEA    	: in std_logic;
	WEB    	: in std_logic;
	RSTA   	: in std_logic;
	RSTB   	: in std_logic;
	CLKA   	: in std_logic;
	CLKB   	: in std_logic;
	ADDRA  	: in std_logic_vector (11 downto 0);
	ADDRB  	: in std_logic_vector (7 downto 0);
	DOA    	: out std_logic_vector (0 downto 0);
	DOB    	: out std_logic_vector (15 downto 0)
    ); 
end component;
--
-- Attribute Decalrations:
-- RAMB4 memory initialization for Alliance (to be written in NCF file)
attribute INIT_00: string;
attribute INIT_01: string;
attribute INIT_02: string;
attribute INIT_03: string;
attribute INIT_04: string;
attribute INIT_05: string;
attribute INIT_06: string;
attribute INIT_07: string;
attribute INIT_08: string;
attribute INIT_09: string;
attribute INIT_0A: string;
attribute INIT_0B: string;
attribute INIT_0C: string;
attribute INIT_0D: string;
attribute INIT_0E: string;
attribute INIT_0F: string;
--
attribute INIT_00 of RAMB4: label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_01 of RAMB4: label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_02 of RAMB4: label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_03 of RAMB4: label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_04 of RAMB4: label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_05 of RAMB4: label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_06 of RAMB4: label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_07 of RAMB4: label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_08 of RAMB4: label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_09 of RAMB4: label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0A of RAMB4: label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0B of RAMB4: label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0C of RAMB4: label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0D of RAMB4: label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0E of RAMB4: label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0F of RAMB4: label is "0000000000000000000000000000000000000000000000000000000000000000";
--
--
-- Signal Declarations:
--
signal DIA_TMP : std_logic_vector(0 downto 0);	-- to match RAMB4 input type
signal BUS16_GND : std_logic_vector(15 downto 0);
-- signal VCC : std_logic;
signal GND : std_logic;
--
begin
-- VCC <= '1';
GND <= '0';
BUS16_GND <= (others =>'0');

DIA_TMP(0) <= DIA;

-- Select BlockRAM RAMB4_S1_S16 instantiation
-- Port A is the Erase  then Write 
-- Port B is the Match 
RAMB4 : RAMB4_S1_S16 
	port map (
	DIA => DIA_TMP,  
	DIB => BUS16_GND ,
	ENA => ENA,
	ENB => ENB,
	WEA => WEA,
	WEB => GND,
	RSTA => GND,
	RSTB => RSTB,
	CLKA => CLK,
	CLKB => CLK,
	ADDRA => ADDRA,
	ADDRB => ADDRB,
--	DOA =>,
	DOB => DOB 
		);
		
end INIT_RAMB4_S1_S16_arch;