display.v

一些vhdl的常用程序

`timescale 1ns/10ps

`define D #1

//===FPGA Training project==//
//==Seven segment display block==//
//==Marshall,2006.04.05==//

module Display(
	/*input*/Reset,Clk128Hz,HourH,HourL,MinH,MinL,SecH,SecL,HourSet,MinSet,Flash,
	/*inout*/
	/*output*/Drive,Sink,AlmOut);
	
input Reset,Clk128Hz;
input [1:0] HourH;
input [2:0] MinH,SecH;
input [3:0] HourL,MinL,SecL;
input HourSet,MinSet;
input Flash;

output [5:0] Drive;
output [0:6] Sink;
output AlmOut;

//==parameters==//
parameter AlmHH = 2'b01;
parameter AlmHL = 4'h2;
parameter AlmMH = 3'h0;
parameter AlmML = 4'h0;

//==regs==//
reg [3:0] DispBuf;
reg [5:0] Drive;
reg [0:6] Sink;

//==wire==//
wire DispBuf0,DispBuf1,DispBuf2,DispBuf3,DispBuf4,DispBuf5,DispBuf6,DispBuf7,DispBuf8,DispBuf9;

//-------------------------------------------------------------------------------------
//==Logic assign==//
assign DispBuf0 = (DispBuf == 4'h0);
assign DispBuf1 = (DispBuf == 4'h1);
assign DispBuf2 = (DispBuf == 4'h2);
assign DispBuf3 = (DispBuf == 4'h3);
assign DispBuf4 = (DispBuf == 4'h4);
assign DispBuf5 = (DispBuf == 4'h5);
assign DispBuf6 = (DispBuf == 4'h6);
assign DispBuf7 = (DispBuf == 4'h7);
assign DispBuf8 = (DispBuf == 4'h8);
assign DispBuf9 = (DispBuf == 4'h9);

assign AlmOut = ((HourH == AlmHH) & (HourL == AlmHL) & (MinH == AlmMH) & (MinL == AlmML)) & Flash;

//==Logic FF==//
//--Drive--//
always @ (posedge Reset or posedge Clk128Hz)
	if (Reset) Drive <= `D 6'h20;
	else if (Drive == 6'h01) Drive <= `D 6'h20;
	else Drive <= `D (Drive >> 1);

//--DispBuf--//
always @ (posedge Reset or posedge Clk128Hz)
	if (Reset) DispBuf <= `D 4'h0;
	else if (Drive[1]) DispBuf <= `D {2'h0,HourH} | {(HourSet & Flash),(HourSet & Flash),(HourSet & Flash),(HourSet & Flash)};
	else if (Drive[0]) DispBuf <= `D HourL | {(HourSet & Flash),(HourSet & Flash),(HourSet & Flash),(HourSet & Flash)};
	else if (Drive[5]) DispBuf <= `D {1'b0,MinH} | {(MinSet & Flash),(MinSet & Flash),(MinSet & Flash),(MinSet & Flash)};
	else if (Drive[4]) DispBuf <= `D MinL | {(MinSet & Flash),(MinSet & Flash),(MinSet & Flash),(MinSet & Flash)};
	else if (Drive[3]) DispBuf <= `D {1'b0,SecH};
	else if (Drive[2]) DispBuf <= `D SecL;
	
//--Sink--//
always @ (posedge Reset or posedge Clk128Hz)
	if (Reset) Sink <= `D 7'h00;
	else if (DispBuf0) Sink <= `D 7'b1000000;
	else if (DispBuf1) Sink <= `D 7'b1111100;
	else if (DispBuf2) Sink <= `D 7'b0010010;
	else if (DispBuf3) Sink <= `D 7'b0010100;
	else if (DispBuf4) Sink <= `D 7'b0101100;
	else if (DispBuf5) Sink <= `D 7'b0000101;
	else if (DispBuf6) Sink <= `D 7'b0000001;
	else if (DispBuf7) Sink <= `D 7'b1011100;
	else if (DispBuf8) Sink <= `D 7'b0000000;
	else if (DispBuf9) Sink <= `D 7'b0001100;	 
														  

endmodule