init_8_ram16x1s.vhd

Using Block RAM for High-Performance Read.Write Cams

--
-- Module: 	INIT_8_RAM16x1s
-- Design: 	CAM_Top
-- VHDL code:	VIRTEX primitives instantiation
--
-- Synthesis	Synopsys FPGA Express ver. 3.2 
--		Use of "pragma synthesis_off/on" and attributes
--
-- Description: Basic building block of a CAM using Select BlockRAM & Select RAM
--		Instantiate 8 RAM16x1s_1 for ERASE operation
--		Initialization of RAM16x1s: attributes to constraint PAR and simulation
--
-- Device: 	VIRTEX Family (VIRTEX & VIRTEX-E)
--		8 x SelectRAM16x1s_1
--
-- Created by: Jean-Louis BRELET / XILINX - VIRTEX Applications
-- Date: July 29, 1999
-- Version: 1.0
--
-- History: 
-- 	1.  JLB-09/24/99 Comment RLOC (optional Placement)
--
--   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
--                WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
--                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
--                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
--  Copyright (c) 1999 Xilinx, Inc.  All rights reserved.
-------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

-- Syntax for Synopsys FPGA Express
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on


entity INIT_8_RAM16x1s is
    port (
	DATA_IN	: in std_logic_vector(7 downto 0) ; 	
	ADDR		: in std_logic_vector(3 downto 0) ;	-- Used by erase/write operation only
	WRITE_RAM	: in std_logic;		-- if '1' DATA_IN is WRITE in the RAM16x1s
	CLK		: in std_logic;
	DATA_WRITE	: out std_logic_vector(7 downto 0) 
	);
end INIT_8_RAM16x1s;

architecture INIT_8_RAM16x1s_arch of INIT_8_RAM16x1s is
--
-- Components Declarations:
-- RAM16x8s macro is not used because the INIT attribute can be specified at the primitive level only.
component RAM16x1s_1
-- RAM initialization for RTL simulation 
-- Syntax for Synopsys FPGA Express
-- pragma synthesis_off
generic( 
      INIT : bit_vector(15 downto 0) := X"0000"
  );
-- pragma synthesis_on	
    port (
	WE	: in std_logic;
	WCLK	: in std_logic; -- inverted Clock
	D	: in std_logic;
	A0	: in std_logic;
	A1	: in std_logic;
	A2	: in std_logic;
	A3	: in std_logic;
	O	: out std_logic
    );
end component;
	
--
-- RAM16x8s memories initialization for Alliance
attribute INIT: string;
attribute INIT of RAM_ERASE_0: label is "0000";
attribute INIT of RAM_ERASE_1: label is "0000";
attribute INIT of RAM_ERASE_2: label is "0000";
attribute INIT of RAM_ERASE_3: label is "0000";
attribute INIT of RAM_ERASE_4: label is "0000";
attribute INIT of RAM_ERASE_5: label is "0000";
attribute INIT of RAM_ERASE_6: label is "0000";
attribute INIT of RAM_ERASE_7: label is "0000";
--
-- Placement of the 8 RAM_ERASE (Optional)
--attribute RLOC: string;
--attribute RLOC of RAM_ERASE_0: label is "R0C0.S1";
--attribute RLOC of RAM_ERASE_1: label is "R0C0.S1";
--attribute RLOC of RAM_ERASE_2: label is "R1C0.S1";
--attribute RLOC of RAM_ERASE_3: label is "R1C0.S1";
--attribute RLOC of RAM_ERASE_4: label is "R2C0.S1";
--attribute RLOC of RAM_ERASE_5: label is "R2C0.S1";
--attribute RLOC of RAM_ERASE_6: label is "R3C0.S1";
--attribute RLOC of RAM_ERASE_7: label is "R3C0.S1";
--
-- Signal Declarations:
--
-- signal VCC : std_logic;
-- signal GND : std_logic;
--
begin
-- VCC <= '1';
-- GND <= '0';

-- SelectRAM instantiation = 8 x RAM16x1s
-- Generate not used because no Initialization by attribute
--RAM_16x8 : for i in 0 to 7 
--generate RAM_ERASE : RAM16x1s_1  
--	port map (
--	WE => WRITE_RAM,
--	WCLK => CLK,
--	D => DATA_IN(i),
--	A0 => ADDR(0),
--	A1 => ADDR(1),
--	A2 => ADDR(2),
--	A3 => ADDR(3),
--	O => DATA_WRITE(i)
--	);
--end generate;
RAM_ERASE_0 : RAM16x1s_1 
	port map (
	WE => WRITE_RAM,
	WCLK => CLK,
	D => DATA_IN(0),
	A0 => ADDR(0),
	A1 => ADDR(1),
	A2 => ADDR(2),
	A3 => ADDR(3),
	O => DATA_WRITE(0)
	);
--
RAM_ERASE_1 : RAM16x1s_1  
	port map (
	WE => WRITE_RAM,
	WCLK => CLK,
	D => DATA_IN(1),
	A0 => ADDR(0),
	A1 => ADDR(1),
	A2 => ADDR(2),
	A3 => ADDR(3),
	O => DATA_WRITE(1)
	);
--
RAM_ERASE_2 : RAM16x1s_1  
	port map (
	WE => WRITE_RAM,
	WCLK => CLK,
	D => DATA_IN(2),
	A0 => ADDR(0),
	A1 => ADDR(1),
	A2 => ADDR(2),
	A3 => ADDR(3),
	O => DATA_WRITE(2)
	);
--
RAM_ERASE_3 : RAM16x1s_1  
	port map (
	WE => WRITE_RAM,
	WCLK => CLK,
	D => DATA_IN(3),
	A0 => ADDR(0),
	A1 => ADDR(1),
	A2 => ADDR(2),
	A3 => ADDR(3),
	O => DATA_WRITE(3)
	);
--
RAM_ERASE_4 : RAM16x1s_1  
	port map (
	WE => WRITE_RAM,
	WCLK => CLK,
	D => DATA_IN(4),
	A0 => ADDR(0),
	A1 => ADDR(1),
	A2 => ADDR(2),
	A3 => ADDR(3),
	O => DATA_WRITE(4)
	);
--
RAM_ERASE_5 : RAM16x1s_1  
	port map (
	WE => WRITE_RAM,
	WCLK => CLK,
	D => DATA_IN(5),
	A0 => ADDR(0),
	A1 => ADDR(1),
	A2 => ADDR(2),
	A3 => ADDR(3),
	O => DATA_WRITE(5)
	);
--
RAM_ERASE_6 : RAM16x1s_1  
	port map (
	WE => WRITE_RAM,
	WCLK => CLK,
	D => DATA_IN(6),
	A0 => ADDR(0),
	A1 => ADDR(1),
	A2 => ADDR(2),
	A3 => ADDR(3),
	O => DATA_WRITE(6)
	);
--
RAM_ERASE_7 : RAM16x1s_1  
	port map (
	WE => WRITE_RAM,
	WCLK => CLK,
	D => DATA_IN(7),
	A0 => ADDR(0),
	A1 => ADDR(1),
	A2 => ADDR(2),
	A3 => ADDR(3),
	O => DATA_WRITE(7)
	);
--
end INIT_8_RAM16x1s_arch;