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FPGA 的代码
comp42_n64.v
`timescale 1ns/10ps
/*-----------------------------------------------------------------------------
$RCSfile: &
$Source: /home/lefurgy/tmp/ISC-repository/isc/hardware/ARM10/behavioral/pipelined/fpga2/
parameters.v
//
// Module: parameters
// Design: CAM_Top
// Verilog code: Defines Parameters for CAM design
//
// Synthesis_tool Synopsys FPGA Express ver. 3.2 - Option = Preserve Hierarchy
// En
test.asm
; http://gforge.openchip.org/projects/a86
;
; First Program being assembled and executed on a86 (FPGA implementation)
; (earlier it was only either simulation run or machine code programs)
;
; In
inport.v
//
// FPGA PACMAN I/O interface
//
// Version : beta1
//
// Copyright(c) 2002 Tatsuyuki Satoh , All rights reserved
//
// Important !
//
// This program is freeware for non-commercial use.
sound.v
//
// FPGA PACMAN waveform sound
//
// Version : beta2
//
// Copyright(c) 2002,2003 Tatsuyuki Satoh , All rights reserved
//
// Important !
//
// This program is freeware for non-commercial u
irq.v
//
// FPGA PACMAN IRQ / vector handler
//
// Version : beta2
//
// Copyright(c) 2002,2003 Tatsuyuki Satoh , All rights reserved
//
// Important !
//
// This program is freeware for non-commer
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity fpga_core_tb is
generic(
idle : integer := 1;
write : integer := 2;
W_and_R : integer := 4;
test.asm
; http://gforge.openchip.org/projects/a86
;
; First Program being assembled and executed on a86 (FPGA implementation)
; (earlier it was only either simulation run or machine code programs)
;
; In
comp42_n64.v
`timescale 1ns/10ps
/*-----------------------------------------------------------------------------
$RCSfile: &
$Source: /home/lefurgy/tmp/ISC-repository/isc/hardware/ARM10/behavioral/pipelined/fpga2/
entries
/ecb_tbl.txt/1.1.1.1/Tue Dec 6 02:47:48 2005//
/xilinx_fpga.ucf/1.1.1.1/Tue Dec 6 02:47:48 2005//
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